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Skylake server introduced a number of {{x86|extensions|new instructions}}: | Skylake server introduced a number of {{x86|extensions|new instructions}}: | ||
− | * {{x86|MPX|<code>MPX</code>}} - Memory Protection Extensions | + | * {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions |
* {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory | * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory | ||
* {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory. | * {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory. |
Facts about "Skylake (server) - Microarchitectures - Intel"
codename | Skylake (server) + |
core count | 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 + and 28 + |
designer | Intel + |
first launched | May 4, 2017 + |
full page name | intel/microarchitectures/skylake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |