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Latest revision | Your text | ||
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*** 1.375 MiB/core, 11-way set associative, shared across all cores | *** 1.375 MiB/core, 11-way set associative, shared across all cores | ||
**** Note that a few models have non-default cache sizes due to disabled cores | **** Note that a few models have non-default cache sizes due to disabled cores | ||
− | *** | + | *** 64 B line size |
*** Non-inclusive victim cache | *** Non-inclusive victim cache | ||
*** Write-back policy | *** Write-back policy | ||
*** 50-70 cycles latency | *** 50-70 cycles latency | ||
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− | |||
* DRAM | * DRAM | ||
** 6 channels of DDR4, up to 2666 MT/s | ** 6 channels of DDR4, up to 2666 MT/s |
Facts about "Skylake (server) - Microarchitectures - Intel"
codename | Skylake (server) + |
core count | 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 + and 28 + |
designer | Intel + |
first launched | May 4, 2017 + |
full page name | intel/microarchitectures/skylake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (server) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |