Editing intel/microarchitectures/saltwell

{{intel title|Saltwell|arch}}
{{microarchitecture
| name          = Saltwell
| manufacturer  = Intel
| introduction  = 2011
| phase-out     = 2013
| process       = 32 nm
| cores         = 1
| cores 2       = 2

| pipeline      = Yes
| type          = Superscalar
| OoOE          = No
| isa           = IA-32
| isa 2         = x86-64
| stages        = 16
| issues        = 2

| inst          = Yes
| feature       = MMX
| extension     = SSE
| extension 2   = SSE2
| extension 3   = SSE3
| extension 4   = SSSE3

| cache         = Yes
| l1i           = 32 KB
| l1i per       = Core
| l1i desc      = 8-way set associative
| l1d           = 24 KB
| l1d per       = Core
| l1d desc      = 6-way set associative
| l2            = 512
| l2 per        = Cores
| l2 desc       = 8-way set associative

| core names       = Yes
| core name        = Penwell
| core name 2      = Cedarview
| core name 3      = Cloverview
| core name 4      = Centerton
| core name 5      = Briarwood
| core name 6      = Berryville

| succession       = Yes
| predecessor      = Bonnell
| predecessor link = intel/bonnell
| successor        = Silvermont
| successor link   = intel/silvermont
}}
'''Saltwell''' was a [[microarchitecture]] for [[Intel]]'s [[32 nm]] ultra-low power [[system on chip]]s first introduced in late 2011 for the {{intel|Atom}} family. Saltwell is a shrink of {{intel|Bonnell}} which also incorporated all support chips on-die. Saltwell, unlike its predecessor was aimed directly at smartphones (as opposed to MIDs).

== Codenames ==
{| class="wikitable"
|-
! Platform !! Core !! Target
|-
| {{intel|Medfield}} || {{intel|Penwell}} || Smartphones
|-
| {{intel|Cedar Trail}} || {{intel|Cedarview}}|| Netbooks
|-
| {{intel|Clover Trail+}} || {{intel|Cloverview}} || Tablets
|-
| {{intel|Bordenville}} || {{intel|Centerton}} || Microservers
|-
| {{intel|Bordenville}} || {{intel|Briarwood}} || Microservers
|-
|  || {{intel|Berryville}} || CE (set-tops)
|-
|}

== Architecture ==
Saltwell's primary goals were:
# Improve on Bonnell by getting rid of older support chips
# Add enhancements using [[32 nm]] process while transitioning to [[22 nm]]
## Improve GPU, power
## Burst frequencies

=== Key changes from Bonnell ===
* L2$ increase rate
* L2$ now seperate rail
* New low-power SRAM for machine state
* Larger instruction fetch
* Double the size of the branch prediction history table
=== Memory Hierarchy ===
* Cache
** Hardware prefetchers
** L1 Cache:
*** 32 KB 8-way [[set associative]] instruction
**** 1 read and 1 write port
*** 24 KB 6-way set associative data
**** 1 read and 1 write port
*** 8 transistors (instead of 6) to reduce voltage
*** Per core
** L2 Cache:
*** 512 KB 8-way set associative
*** ECC
*** Shrinkable from 512 KB to 128 KB (2-way)
*** 32B/cycle and 32 outstanding cache requests
*** separate voltage rail, fixed @ 1.05V
*** Per core
** L3 Cache:
*** No level 3 cache
** Non-Cache Shared State Memory
*** 256KB low-power SRAM
*** separate voltage plane
*** always-on block that stores architectural states while in various power saving modes
** RAM
*** Maximum of 1GB, 2 GB, and 4 GB
*** dual 32-bit channels, 1 or 2 ranks per channel

=== Functional Units ===
The number of functional units were kept to minimum to cut on power consumption.
* 2 Integer [[ALU]]s (1 for jumps, 1 for shifts)
* 2 FP ALUs (1 adder, 1 for others)
* No Integer multiplier & divider
=== Pipeline ===
Saltwell has an almost identical pipeline to {{intel|Bonnell|Bonnell's}} with a 16-stage pipeline with a 13-stage miss penalty. It's also still a dual-issue [[superscalar]] but with in-order execution. Reordering logic is was still omitted due to power and area restrictions.

:[[File:bonnell pipeline.svg]]

The longer pipeline allows a more evenly spreading of heat across the chip with more units. This also allows a higher clock rate. 

* '''Instruction Fetch'''
** 3 stages
** 48 Bytes/Cycle (lower if SMT)
* '''Instruction Decode'''
** 3 stages
** Instructions with up to 3 prefixes/Cycle
* '''Instruction Dispatch'''
** 2 stages
* '''Source Operand Read'''
** 1 stage
*** reading [[register]] operand
* '''Data Cache Access'''
** 3 stages
*** 1 stage for calculating
*** 2 stages for reading cache
* '''Execution'''
** 2 clusters
*** integers
**** quick cache access due to direct connection
*** floating point & SIMD
* '''Exception & MT Handling'''
** 2 stages
* '''Commit'''
** 1 stage

=== Multithreading ===
Saltwell has support for multithreading - up to two threads per core. However each thread compete for the same resources which does inherently means they run slower than they would if they were to run alone.

=== Branch Prediction ===
* [[Two-level adaptive predictor]]
* 12-bit branch history register 
* Pattern history table has 8192 entries (shared between threads), twice that of {{intel|Bonnell}}
* Branch buffer target has 128 entries (4-way, 32 sets)
* Unconditional jumps are ignored
* Always-taken and never-taken are marked in the table
* Penalties:
** 13 stages for miss prediction
** 7 stages for correct prediction but missing [[branch target buffer]] (BTB)

== Cores ==
* '''{{intel|Penwell}}''' - SoCs specifically for smartphones
* '''{{intel|Cedarview}}''' - SoCs for netbooks
* '''{{intel|Cloverview}}''' - SoCs for tablets
* '''{{intel|Centerton}}''' - SoCs for Microservers; added support for Intel VT and ECC memory
* '''{{intel|Briarwood}}''' - SoCs for Microservers
* '''{{intel|Berryville}}''' - SoCs for consumer electronics (e.g. set-tops)
codename	Saltwell +
core count	1 + and 2 +
designer	Intel +
first launched	2011 +
full page name	intel/microarchitectures/saltwell +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Saltwell +
phase-out	2013 +
pipeline stages	16 +
process	32 nm (0.032 μm, 3.2e-5 mm) +