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The RIB serves as the interface between the core and the router and performances the necessary synchronizations of data transfers and the power management (e.g., since the core may be stalling on data). 38-bit FLITs get buffered in a 16-entry queue where they get multiplexed and routed to either the D$ (64-bit packets) or I$ (96-bit packet) based on the lane ID field of the FLIT. Note that buffering is done because register file stores to the data cache have priority over the RIB. FLIT1 gets decoded and several control signals are generated, allowing the program execution (REN) to start at the specific address (PCA) through the new program counter bit (NPC).
 
The RIB serves as the interface between the core and the router and performances the necessary synchronizations of data transfers and the power management (e.g., since the core may be stalling on data). 38-bit FLITs get buffered in a 16-entry queue where they get multiplexed and routed to either the D$ (64-bit packets) or I$ (96-bit packet) based on the lane ID field of the FLIT. Note that buffering is done because register file stores to the data cache have priority over the RIB. FLIT1 gets decoded and several control signals are generated, allowing the program execution (REN) to start at the specific address (PCA) through the new program counter bit (NPC).
  
Note that the RIB is also in charge of the power management during WAKE and SLEEP instructions and can put the entire core into sleep or wake it up depending on the incoming or outgoing packets.
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Note that the RIB is also in charge of the power management during WAKE and SLEEP instructions and can put the entire code into sleep or wake it up depending on the incoming or outgoing packets.
  
 
== Freya (SRAM) ==
 
== Freya (SRAM) ==

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codenamePolaris +
core count80 +
designerIntel +
first launchedFebruary 2007 +
full page nameintel/microarchitectures/polaris +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeCPU +
namePolaris +
pipeline stages9 +
process65 nm (0.065 μm, 6.5e-5 mm) +