Difference between revisions of "intel/microarchitectures/merced"

Revision as of 02:29, 20 January 2021

Merced was the first Itanium microarchitecture designed by Intel.

10 stage pipeline
- IPG: Get next instruction pointer
- FET: Fetch from instruction cache
- ROT: Instruction rotation, decoupling buffer
- EXP: Instruction dispersal
- REN: Register remapping
- WLD: Word line decode
- REG: Register file read
- EXE: Execute
- DET: Exception detection
- WRB: Writeback
Branch Predictor
- Early zero bubble predictor using Target Address Registers controlled by the compiler
- Two-level predictor with 4 bits of local history and a 512 entry prediction table
- Indirect branches handled with 64 entry Multiway Branch Prediction Table
- 64-entry Target Address Cache
- 8 entry Return Address Stack
- Branch predictor can resteer at ROT stage using the loop exit predictor, or compiler provided prediction hints for the third slot in a bundle.
- Branch predictor can resteer at EXP stage for any branch
16K 4-way L1 Instruction Cache
Fetch and Decode
- Two bundles, each containing three instructions, fetched from the instruction cache every cycle
- No decoder necessary

Block diagram of Merced

@@ Line 54: / Line 54: @@
 }}
 '''Merced''' was the first [[Itanium]] microarchitecture designed by [[Intel]].
+== Architecture ==
+* 10 stage pipeline
+** IPG: Get next instruction pointer
+** FET: Fetch from instruction cache
+** ROT: Instruction rotation, decoupling buffer
+** EXP: Instruction dispersal
+** REN: Register remapping
+** WLD: Word line decode
+** REG: Register file read
+** EXE: Execute
+** DET: Exception detection
+** WRB: Writeback
+* Branch Predictor
+** Early zero bubble predictor using Target Address Registers controlled by the compiler
+** Two-level predictor with 4 bits of local history and a 512 entry prediction table
+** Indirect branches handled with 64 entry Multiway Branch Prediction Table
+** 64-entry Target Address Cache
+** 8 entry Return Address Stack
+** Branch predictor can resteer at ROT stage using the loop exit predictor, or compiler provided prediction hints for the third slot in a bundle.
+** Branch predictor can resteer at EXP stage for any branch
+* 16K 4-way L1 Instruction Cache
+* Fetch and Decode
+** Two bundles, each containing three instructions, fetched from the instruction cache every cycle
+** No decoder necessary
+[[File:merced.png|thumb|Block diagram of Merced]]

codename	Merced +
core count	1 +
designer	Intel +
first launched	June 2001 +
full page name	intel/microarchitectures/merced +
instance of	microarchitecture +
instruction set architecture	IA-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Merced +
process	180 nm (0.18 μm, 1.8e-4 mm) +