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Latest revision Your text
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|stages min=14
 
|stages min=14
 
|stages max=19
 
|stages max=19
−
|isa=x86-64
+
|isa=x86-16
 +
|isa 2=x86-32
 +
|isa 3=x86-64
 
|extension=MOVBE
 
|extension=MOVBE
 
|extension 2=MMX
 
|extension 2=MMX
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|extension 29=SGX
 
|extension 29=SGX
 
|extension 30=MPX
 
|extension 30=MPX
 +
|extension 31=AVX-512
 
|l1i=32 KiB
 
|l1i=32 KiB
 
|l1i per=core
 
|l1i per=core
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|core name=Kaby Lake Y
 
|core name=Kaby Lake Y
 
|core name 2=Kaby Lake U
 
|core name 2=Kaby Lake U
−
|core name 3=Kaby Lake R
+
|core name 3=Kaby Lake H
−
|core name 4=Kaby Lake H
+
|core name 4=Kaby Lake S
−
|core name 5=Kaby Lake G
+
|core name 5=Kaby Lake DT
−
|core name 6=Kaby Lake S
+
|core name 6=Kaby Lake X
−
|core name 7=Kaby Lake DT
 
−
|core name 8=Kaby Lake X
 
 
|predecessor=Skylake
 
|predecessor=Skylake
 
|predecessor link=intel/microarchitectures/skylake
 
|predecessor link=intel/microarchitectures/skylake
 
|successor=Coffee Lake
 
|successor=Coffee Lake
 
|successor link=intel/microarchitectures/coffee lake
 
|successor link=intel/microarchitectures/coffee lake
−
|successor 2=Cannon Lake
+
|successor 2=Cannonlake
−
|successor 2 link=intel/microarchitectures/cannon lake
+
|successor 2 link=intel/microarchitectures/cannonlake
 +
|pipeline=Yes
 +
|OoOE=Yes
 +
|issues=5
 +
 
 +
 
 +
|core names=Yes
 +
 
 
}}
 
}}
−
[[File:7th Gen Core-i7-badge.png|thumb|right|175px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]]
+
[[File:7th Gen Core-i7-badge.png|thumb|right|250px|Kaby Lake is Intel's 7th Generation {{intel|Core i7}} MPUs.]]
−
'''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannon Lake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannon Lake being pushed back to [[2018]]).  
+
'''Kaby Lake''' ('''KBL''') is [[Intel]]'s successor to {{\\|Skylake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. {{\\|Cannonlake}} was originally set to replace {{\\|Skylake}} as the next microarchitecture using a [[10 nm process]], however Intel later revised their roadmap to include Kaby Lake (with Cannonlake being pushed back to [[2017]]).  
  
−
For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For workstation class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}. There are no Kaby Lake-based server microprocessors.
+
For desktop and mobile, Kaby Lake is branded as 7th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v6}}, {{intel|Xeon E5|Xeon E5 v6}}, and {{intel|Xeon E7|Xeon E7 v6}}.
  
 
== Codenames ==
 
== Codenames ==
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
−
! Core !! Abbrev !! Platform || Description !! Graphics !! Target
+
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
|-
−
| {{intel|Kaby Lake Y|l=core}} || KBL-Y || || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
+
| {{intel|Kaby Lake Y|l=core}} || KBL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
|-
 
|-
−
| {{intel|Kaby Lake U|l=core}} || KBL-U || || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
+
| {{intel|Kaby Lake U|l=core}} || KBL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|-
 
|-
−
| {{intel|Kaby Lake R|l=core}} || KBL-R || || Ultra-low Power || GT2 || Kaby Lake U Refresh
+
| {{intel|Kaby Lake H|l=core}} || KBL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
 
|-
 
|-
−
| {{intel|Kaby Lake H|l=core}} || KBL-H || || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
+
| {{intel|Kaby Lake S|l=core}} || KBL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
 
|-
 
|-
−
| {{intel|Kaby Lake S|l=core}} || KBL-S || || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
+
| {{intel|Kaby Lake R|l=core}} || KBL-R || || || Kaby Lake U Refresh?
 
|-
 
|-
−
| {{intel|Kaby Lake G|l=core}} || KBL-G || {{intel|Pedlow|l=platform}} || Gaming Chip || GT2 + AMD {{amd|Vega|l=arch}} || Kaby Lake + Radeon Vega 20/24
+
| {{intel|Kaby Lake G|l=core}} || KBL-G || || || Kaby Lake + ?
 
|-
 
|-
−
| {{intel|Kaby Lake X|l=core}} || KBL-X || {{intel|Basin Falls|l=platform}} || Extreme Performance || || High-end desktops & enthusiasts market
+
| {{intel|Kaby Lake X|l=core}} || KBL-X || Extreme Performance || || High-end desktops & enthusiasts market
 
|-
 
|-
−
| {{intel|Kaby Lake DT|l=core}} || KBL-DT || {{intel|Greenlow|l=platform}} || Workstation || GT2 || Workstations & entry-level servers
+
| {{intel|Kaby Lake DT|l=core}} || KBL-DT || Workstation || GT2 || Workstations & entry-level servers
 
|}
 
|}
  
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
|-
 
|-
−
| [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
+
| [[File:intel celeron (2015).png|50px]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
−
|-
 
−
| rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
 
−
|-
 
−
| style="text-align: left;" | Budget (Desktop) || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
 
−
|-
 
−
| rowspan="2" | [[File:intel pentium gold logo (2017).png|50px|link=intel/pentium_gold]] || rowspan="2" | {{intel|Pentium Gold}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
 
 
|-
 
|-
−
| style="text-align: left;" | Budget (Desktop) || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
+
| rowspan="2" | [[File:intel pentium (2015).png|50px]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
| rowspan="2" | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || rowspan="2" | {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" | dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
+
| style="text-align: left;" | Budget (Desktop) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔
 
|-
 
|-
−
| style="text-align: left;" | Low-end Performance (E Series) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
+
| rowspan="2" | [[File:core i3 logo (2015).png|50px]] || rowspan="2" |  {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" |  dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
| rowspan="3" | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || rowspan="3" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
+
| style="text-align: left;" | Low-end Performance (E Series) || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔
 
|-
 
|-
−
| rowspan="2" | [[quad-core|quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
+
| rowspan="2" | [[File:core i5 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
| style="text-align: left;" | Mid-range Performance ({{intel|Kaby Lake R|KBL-R|l=core}}) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
+
|[[quad-core|quad]] || style="background-color: #ffdad6;" | ✘ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
| rowspan="2" | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || rowspan="2" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
+
| rowspan="2" | [[File:core i7 logo (2015).png|50px]] || rowspan="2" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
|quad || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
+
|quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘
 
|-
 
|-
−
| [[File:xeon logo (2015).png|50px|link=intel/xeon e3]] ||  {{intel|Xeon E3}} || style="text-align: left;" | Workstation high-performance/dense servers || quad || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
+
| [[File:xeon logo (2015).png|50px]] ||  {{intel|Xeon E3}} || style="text-align: left;" | Workstation high-performance/dense servers || quad || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔
 
|}
 
|}
  
 
== Release Dates ==
 
== Release Dates ==
−
Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. The enthusiast version, {{intel|Kaby Lake X|l=core}}, was introduced during Computex Taipei 2017.
+
Kaby Lake is set to be released in two phases. The first phase was announced in August of [[2016]] and was primarily aimed at various low-power consumer products such as light notebooks and 2-in-1s. Those devices are powered by {{intel|Kaby Lake Y|l=core}} and {{intel|Kaby Lake U|l=core}} CPUs. Intel released mainstream {{intel|Kaby Lake S|l=core}} and {{intel|Kaby Lake H|l=core}} processors on January 3, [[2017]] in time for CES 2017. Additionally, {{intel|Kaby Lake X|l=core}} are expecting to be released in late August during Gamescom 2017.
−
 
 
−
On August 21 2017, Intel introduced 8th generation mobile processors ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}}) which is also based on the same microarchitecture and doubled the cores (4 from 2) of many mainstream mobile microprocessors.
 
  
 
== Process Technology ==
 
== Process Technology ==
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== Compatibility ==
 
== Compatibility ==
−
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. [[Microsoft]] announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.
+
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. Microsoft announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.
  
 
{| class="wikitable"
 
{| class="wikitable"
 
! Vendor !! OS  !! Version !! Notes
 
! Vendor !! OS  !! Version !! Notes
 
|-
 
|-
−
| rowspan="3" | [[Microsoft]] || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
+
| rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
 
|-
 
|-
 
| style="background-color: #ffdad6;" | Windows 8 || No Support
 
| style="background-color: #ffdad6;" | Windows 8 || No Support
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=== CPUID ===
 
=== CPUID ===
−
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
+
{| class="wikitable tc1 tc2 tc3 tc4"
−
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
+
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
−
| rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}}/{{intel|Kaby Lake R|R|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0x9
+
| rowspan="2" | {{intel|Kaby Lake Y|Y|l=core}}/{{intel|Kaby Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE
 
|-
 
|-
−
| colspan="5" | Family 6 Model 142 Stepping 9
+
| colspan="4" | Family 6 Model 142
 
|-
 
|-
−
| rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE || 0x9
+
| rowspan="2" | {{intel|Kaby Lake DT|DT|l=core}}/{{intel|Kaby Lake H|H|l=core}}/{{intel|Kaby Lake S|S|l=core}}/{{intel|Kaby Lake X|X|l=core}} || 0 || 0x6 || 0x9 || 0xE
 
|-
 
|-
−
| colspan="5" | Family 6 Model 158 Stepping 9
+
| colspan="4" | Family 6 Model 158
 
|}
 
|}
  
 
== Architecture ==
 
== Architecture ==
 
{{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}}
 
{{see also|intel/microarchitectures/skylake#Key_changes_from_Broadwell|l1=Skylake § Key changes from Broadwell}}
 +
[[File:kaby lake silicon wafer.jpg|right|thumb|Kaby Lake silicon [[wafer]] with 7th generation core processor dies.]]
 
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models such as the [[Core i7-7700K]] capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup.
 
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of enhancements in Kaby Lake. Note that because of the improvements done to the process and the uplift in binning, it is the mostly the ultra-low power (i.e. mobile) processors that will see the most substantial gain. Likewise, the high-end models will see very little gain. The enhanced manufacturing process allowed Kaby Lake chips to be highly [[overclockable]] with models such as the [[Core i7-7700K]] capable of comfortably reaching 5 GHz for many people with a reasonable cooling setup.
  
Line 225: Line 226:
 
*** Sunrise Point is still compatible (may need firmware update)
 
*** Sunrise Point is still compatible (may need firmware update)
 
** Added support for {{intel|Optane}} Technology
 
** Added support for {{intel|Optane}} Technology
−
 
−
* Memory
 
−
** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (from DDR4-2133)
 
−
** Faster memory for high-perf mobile (i.e., {{intel|Kaby Lake H|l=core}}) DDR4-2400 (from DDR4-2133)
 
  
 
* Interfaces
 
* Interfaces
Line 234: Line 231:
  
 
* {{intel|Gen 9.5|l=arch}} GPUs
 
* {{intel|Gen 9.5|l=arch}} GPUs
−
** Iris Plus now support HDMI (1.4a) 4096x2304 @ 30 Hz (from 24 Hz)
 
 
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]])
 
** New native hardware support for 4K HEVC/VP9 (See [[#Graphics|§ Graphics]])
 
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change)
 
** {{intel|HD Graphics 510}} '''→''' {{intel|HD Graphics 610}} (12 Execution Units, no change)
Line 245: Line 241:
  
 
* Families
 
* Families
−
** {{intel|Core i3}} processors dropped support for ECC memory in some models
+
** {{intel|Core i3}} processors dropped support for ECC memory (except for Embedded models)
 
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.)
 
** {{intel|Pentium (2009)|Pentium}} desktop processors now have {{intel|Hyper-Threading}} support (note that Mobile Pentium already had that feature.)
 
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support
 
** {{intel|Pentium (2009)|Pentium}} desktop & mobile processors now have Memory Protection ({{intel|MPX}}) and {{intel|OS Guard}} support
Line 258: Line 254:
  
 
==== Individual Core ====
 
==== Individual Core ====
−
<small>(Core identical to {{\\|Skylake (client)}})</small>
+
<small>(Core identical to {{\\|Skylake}})</small>
  
−
[[File:skylake block diagram.svg|900px]]
+
[[File:skylake block diagram.svg]]
  
 
==== Gen9.5 ====
 
==== Gen9.5 ====
Line 332: Line 328:
 
**** fixed partition
 
**** fixed partition
 
*** 1G page translations:
 
*** 1G page translations:
−
**** 4 entries; 4-way set associative
+
**** 4 entries; fully associative
 
**** fixed partition
 
**** fixed partition
 
** STLB
 
** STLB
Line 342: Line 338:
 
**** fixed partition
 
**** fixed partition
 
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
 
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
−
 
−
 
−
* '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Kaby Lake erratum KBL096 recommends software to simply ignore that value.
 
  
 
== Core ==
 
== Core ==
−
{{main|intel/microarchitectures/skylake#Core|l1=Skylake § Core}}
 
−
Kaby Lake's core is identical to {{\\|Skylake#Core|Skylake's}}.
 
−
 
 
=== Pipeline ===
 
=== Pipeline ===
 
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
 
{{main|intel/microarchitectures/skylake#Pipeline|l1=Skylake § Pipeline}}
 
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.
 
Kaby Lake's pipeline is identical to {{\\|Skylake#Pipeline|Skylake's}}.
  
−
== Configurability ==
+
==== Scheduler Ports & Execution Units ====
 +
<table class="wikitable">
 +
<tr><th colspan="2">Scheduler Ports Designation</th></tr>
 +
<tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr>
 +
<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
 +
<tr><td>Integer/FP Division and [[Square Root]]</td></tr>
 +
<tr><td>[[AES]] Encryption</td></tr>
 +
<tr><td>Branch2</td></tr>
 +
<tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr>
 +
<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
 +
<tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr>
 +
<tr><td>Vector Permute</td></tr>
 +
<tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr>
 +
<tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr>
 +
<tr><td>Branch</td></tr>
 +
<tr><th>Port 2</th><td>Load, AGU</td></tr>
 +
<tr><th>Port 3</th><td>Load, AGU</td></tr>
 +
<tr><th>Port 4</th><td>Store, AGU</td></tr>
 +
<tr><th>Port 7</th><td>AGU</td></tr>
 +
</table>
  
−
Kaby Lake builds upon the Skylake architecture, most dies are slight enhancements of their Skylake counterparts. The biggest change is the removal of the high performance quad core GT4 die, which has been replaced by the Kaby Lake G processors. And the introduction of the first low power quad core processor.
+
{| class="wikitable collapsible collapsed"
−
+
|-
−
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:right">
+
! colspan="3" | Execution Units
−
File:2 core lp gt2 skylake.svg|Dual-core die, GT2 GPU, Low Power
+
|-
−
File:2 core lp gt3 skylake.svg|Dual-core die, GT3 GPU, Low Power
+
! Execution Unit !! # of Units !! Instructions
−
File:4 core lp gt2 kabylake.svg|Quad-core die, GT2 GPU, Low Power
+
|-
−
File:dual core hp gt2 skylake.svg|Dual-core die, GT2 GPU, High Power
+
| ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
−
File:4 core hp gt2 skylake.svg|Quad-core die, GT2 GPU, High Power
+
|-
−
</gallery>
+
| DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
−
 
+
|-
−
{{clear}}
+
| Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc...
 +
|-
 +
| Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
 +
|-
 +
| Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc...
 +
|-
 +
| Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc
 +
|-
 +
| FP Mov || 1 || (v)movsd/ss, (v)movd gpr
 +
|-
 +
| SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
 +
|-
 +
| Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
 +
|-
 +
| Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8
 +
|-
 +
| Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
 +
|-
 +
| Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd*
 +
|-
 +
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 +
|}
  
 
== Graphics ==
 
== Graphics ==
 
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
 
{{main|intel/microarchitectures/gen9.5|l1=Gen9.5}}
−
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, and [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).
+
Support for three displays via [[HDMI]] 1.4<ref group=graphics>Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an [[LSPCON]] ([[Level Shifter]]/[[Protocol Converter]]) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.</ref>, [[DisplayPort]] (DP) 1.2, an [[Embedded DisplayPort]] (eDP) 1.4 interfaces. Kaby Lake's biggest enhancement is the addition of native [[fixed function]] HEVC/VP9 decoding for 4K playback at 60fps (10-bit) as well as [[fixed function]] HEVC/VP9 encoding for 4K (8-bit).
  
 
{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
Line 380: Line 410:
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
−
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" rowspan="7" | '''2.0'''
+
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" rowspan="7" | '''2.0'''
 
|-
 
|-
 
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
 
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
 
|-
 
|-
−
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}}, {{intel|Kaby Lake R|R}} || -
+
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
 
|-
 
|-
 
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
 
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
Line 405: Line 435:
 
! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus
 
! !! Core !! Socket !! Permanent !! Platform !! Chipset !! Bus
 
|-
 
|-
−
| [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="3" | N/A || rowspan="3" | OPI
+
| [[File:kaby lake y (back).png|100px|link=intel/cores/kaby_lake_y]] || {{intel|Kaby Lake Y|l=core}} || {{intel|BGA-1515}} || Yes || 1-chip || rowspan="2" | N/A || rowspan="2" | OPI
 
|-
 
|-
−
| [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} || rowspan="2" | {{intel|BGA-1356}} || rowspan="2" | Yes || rowspan="2" | 1-chip
+
| [[File:kaby lake u (back; standard).png|100px|link=intel/cores/kaby_lake_u]] || {{intel|Kaby Lake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip
−
|-
 
−
| [[File:kaby lake r (back).png|100px|link=intel/cores/kaby_lake_r]] || {{intel|Kaby Lake R|l=core}}
 
 
|-
 
|-
 
| [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]]
 
| [[File:kaby lake h (back).png|100px|link=intel/cores/kaby_lake_h]] || {{intel|Kaby Lake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}}<ref group="c">Requires a firmware update in order to work with Kaby Lake chips</ref><br>{{intel|Union Point}} || rowspan="4" | [[DMI 3.0]]
Line 417: Line 445:
 
| {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}}
 
| {{intel|Kaby Lake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}}<br>Xeon {{intel|Union Point}}
 
|-
 
|-
−
| [[File:skylake x (back).png|100px|link=intel/cores/kaby_lake_x]] || {{intel|Kaby Lake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}}
+
| &nbsp; || {{intel|Kaby Lake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}}
 
|}
 
|}
  
 
<references group="c" />
 
<references group="c" />
−
 
−
 
−
=== Packages ===
 
−
{| class="wikitable"
 
−
|-
 
−
! Core !! Die Type !! Package !! Dimensions
 
−
|-
 
−
| {{intel|Kaby Lake H|l=core}} || 4+2 || rowspan="2" | {{intel|FCBGA-1440}} || rowspan="2" | 42 mm x 28 mm x 1.46 mm
 
−
|-
 
−
| {{intel|Kaby Lake H|l=core}} || 2+2
 
−
|-
 
−
| {{intel|Kaby Lake S|l=core}} || 4+2 || rowspan="2" | {{intel|FCLGA-1151}} || rowspan="2" | 37.5 mm x 37.5 mm x 4.4 mm
 
−
|-
 
−
| {{intel|Kaby Lake S|l=core}} || 2+2
 
−
|}
 
  
 
== Clock domains ==
 
== Clock domains ==
Line 451: Line 464:
 
=== Overclocking ===
 
=== Overclocking ===
 
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}.
 
See {{intel|Skylake#Overclocking|Skylake §Overclocking|l=arch}}.
−
 
−
== Kaby Lake G ==
 
−
[[File:kaby lake g with amd radeon package.png|right|300px]]
 
−
{{main|intel/cores/kaby lake g|l1=Kaby Lake G Core}}
 
−
At CES 2018 (January 7) Intel announced ''8th Gen Intel Core with Radeon RX Vega M'', formerly code name {{intel|Kaby Lake G|l=core}}. Those parts combine Intel's {{intel|Kaby Lake H|l=core}} parts with and [[AMD]] {{amd|Vega|l=arch}} GPU as well as [[high-bandwidth memory]] 2.
 
−
 
−
All parts incorporate 4 GiB of [[HBM 2]] along with an [[AMD]] {{amd|Vega|l=arch}} GPU. The HBM2 and GPU are interconnected using Intel's [[EMIB]], however, the CPU and GPU are connected using standard in-package wires over standard PCIe 3.0. x8 lanes are permanently reserved for direct GPU-CPU communication. This leaves x8 additional lanes for all other peripherals that need direct connection to the CPU.
 
−
 
−
[[File:intel-radeon emib solution.svg|650px]]
 
−
 
−
Intel claims that the use of HBM2 instead of [[GDDR5]] results in 80% less power. It's worth noting that since those are {{intel|Kaby Lake H|l=core}} parts with {{amd|Radeon}} Graphics, they effectively have two GPUs and both GPUs are usable. Fairly significant power saving can be achieved by defaulting to the integrated graphics when high performance is not required. In total there are 3 display outputs from the integrated graphics and an additional 6 outputs from the Radeon graphics for a total of 9.
 
−
 
−
By moving from [[GDDR5]] to [[HBM 2]] and going to higher integration by packing everything into a single package, Intel has achieved considerably higher density. Intel reported that around 1900 mm² (~3 in²) board space saving has been achieved which is rather significant for ultra-light and ultra-thin notebooks and tablets where logic board area reduction is important. Additionally, this reduces the [[bills of material|BOM]] for OEMs.
 
−
 
−
[[File:kaby lake g board space saving.png|700px]]
 
−
 
−
=== Dynamic Tuning ===
 
−
[[File:intel dynamic tuning.png|right|250px]]
 
−
{{main|intel/dynamic tuning|l1=Dynamic Tuning}}
 
−
With Kaby Lake G Intel introduced Dynamic Tuning which is a way of managing the entire package power consumption by adjusting the power policies of the GPU and CPU depending on the application. Applications that make no use of the discrete GPU will see the majority of the package power budget allocated for the CPU to accelerate that workloads while things like gaming will shift the power in favor of GPU acceleration. The feature is implemented entirely in software.
 
−
 
−
=== Graphics ===
 
−
{{intel|Kaby Lake G|l=core}} has one of two possible AMD {{amd|Radeon}} graphics based on the {{amd|Vega|l=arch}} microarchitecture.
 
−
 
−
{| class="wikitable"
 
−
! colspan="3" | Radeon RX Vega
 
−
|-
 
−
! Graphics !! Radeon RX Vega M GH !! Radeon RX Vega M GL
 
−
|-
 
−
| Architecture || {{amd|Vega|Vega M|l=arch}} || {{amd|Vega|Vega M|l=arch}}
 
−
|-
 
−
| Compute Units || 24 || 20
 
−
|-
 
−
| Stream Processors || 1,536 || 1,280
 
−
|-
 
−
| ROPs || 64 pixels/clock || 32 pixels/clock
 
−
|-
 
−
| Base Clock || 1,063 MHz || 931 MHz
 
−
|-
 
−
| Boost Frequency || 1,190 MHz || 1,011 MHz
 
−
|-
 
−
| Peak Performance || 3.7 TFLOPS || 2.6 TFLOPS
 
−
|-
 
−
! colspan="3" | HBM 2
 
−
|-
 
−
| Capacity || 4 GiB || 4 GiB
 
−
|-
 
−
| Clock || 800 MHz || 700 MHz
 
−
|-
 
−
| Bandwidth || 204.8 GB/s || 179.2 GB/s
 
−
|}
 
  
 
== Die ==
 
== Die ==
Line 524: Line 486:
 
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa.png|150px]]</div>
 
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa.png|150px]]</div>
 
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa (annotated).png|150px]]</div>
 
<div style="float: left;  margin: 10px;">[[File:kaby lake 4c sa (annotated).png|150px]]</div>
−
</div>
 
−
<div style="text-align: center; display: inline-block;">
 
−
'''Quad-Core ({{intel|Kaby Lake R|l=core}}) Die'''
 
−
<div style="float: left;  margin: 10px;">[[File:kaby lake r sa.png|150px]]</div>
 
−
<div style="float: left;  margin: 10px;">[[File:kaby lake r sa (annotated).png|150px]]</div>
 
 
</div>  
 
</div>  
 
</div>
 
</div>
Line 563: Line 520:
 
* [[14 nm process|14 nm+ process]]
 
* [[14 nm process|14 nm+ process]]
 
* 11 metal layers
 
* 11 metal layers
−
* ~9,21 mm x ~13,50 mm
 
−
* ~126 mm² die size
 
 
* 4 CPU cores + 24 GPU EUs
 
* 4 CPU cores + 24 GPU EUs
  
−
: [[File:kaby lake (quad core).png|class=wikichip_ogimage|650px]]
+
: [[File:kaby lake (quad core).png|650px]]
  
  
 
: [[File:kaby lake (quad core) (annotated).png|650px]]
 
: [[File:kaby lake (quad core) (annotated).png|650px]]
−
 
−
=== Quad-Core (Mobile {{intel|Kaby Lake R|l=core}}) ===
 
−
With the introduction of {{intel|Kaby Lake R|l=core}}, a new quad-core die was introduced. It's worth pointing out that this die is very different from the standard desktop quad-core die. Other than likely being optimized specifically for this market segment, this die also incorporates {{\\|Skylake (client)#Image Processing Unit (IPU)|the IPU}} in the System Agent. Previously this integration was only found in the dual-core dies which were used for {{intel|Skylake U|l=core}} and {{intel|Kaby Lake U|l=core}}.
 
−
 
−
* [[14 nm process|14 nm+ process]]
 
−
* 11 metal layers
 
−
* 123 mm² die size
 
−
* 4 CPU cores + 24 GPU EUs
 
−
 
−
: [[File:kaby lake r die shot.png|650px]]
 
−
 
−
 
−
: [[File:kaby lake r die shot (annotated).png|650px]]
 
−
 
−
=== Additional Shots ===
 
−
Additional die and wafer shots provided by Intel:
 
−
 
−
<gallery mode=slideshow>
 
−
File:kaby lake silicon wafer.jpg|Kaby Lake silicon [[wafer]] with 7th generation core processor dies.
 
−
File:intel kaby lake r wafer.png|Wafer shot of {{intel|Kaby Lake R|l=core}}, 8th generation core.
 
−
</gallery>
 
  
 
== All Kaby Lake Chips ==
 
== All Kaby Lake Chips ==
Line 607: Line 541:
 
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th>Platform</th><th>Core</th><th data-sort-type="number">Cores</th><th data-sort-type="number">Threads</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>[[ECC]]</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
 
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">[[Uniprocessors]]</th></tr>
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::!Kaby Lake R]][[core name::!Kaby Lake G]]
+
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]]
−
|?full page name
 
−
|?model number
 
−
|?first launched
 
−
|?release price
 
−
|?microprocessor family
 
−
|?platform
 
−
|?core name
 
−
|?core count
 
−
|?thread count
 
−
|?l3$ size
 
−
|?l4$ size
 
−
|?tdp
 
−
|?base frequency#GHz
 
−
|?turbo frequency (1 core)#GHz
 
−
|?max memory#GiB
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|?has_ecc_memory_support
 
−
|?has intel turbo boost technology 2_0
 
−
|?has simultaneous multithreading
 
−
|?has advanced vector extensions
 
−
|?has advanced vector extensions 2
 
−
|?has intel trusted execution technology
 
−
|?has transactional synchronization extensions
 
−
|?has intel vpro technology
 
−
|?has_intel_vt-d_technology
 
−
|format=template
 
−
|template=proc table 3
 
−
|searchlabel=
 
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
|userparam=27:19
 
−
|mainlabel=-
 
−
|limit=100
 
−
}}
 
−
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">8th Generation ({{intel|Kaby Lake R|Kaby Lake Refresh|l=core}})</th></tr>
 
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake R]]
 
−
|?full page name
 
−
|?model number
 
−
|?first launched
 
−
|?release price
 
−
|?microprocessor family
 
−
|?platform
 
−
|?core name
 
−
|?core count
 
−
|?thread count
 
−
|?l3$ size
 
−
|?l4$ size
 
−
|?tdp
 
−
|?base frequency#GHz
 
−
|?turbo frequency (1 core)#GHz
 
−
|?max memory#GiB
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|?has_ecc_memory_support
 
−
|?has intel turbo boost technology 2_0
 
−
|?has simultaneous multithreading
 
−
|?has advanced vector extensions
 
−
|?has advanced vector extensions 2
 
−
|?has intel trusted execution technology
 
−
|?has transactional synchronization extensions
 
−
|?has intel vpro technology
 
−
|?has_intel_vt-d_technology
 
−
|format=template
 
−
|template=proc table 3
 
−
|searchlabel=
 
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
|userparam=27:19
 
−
|mainlabel=-
 
−
|limit=100
 
−
}}
 
−
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="25">8th Generation ({{intel|Kaby Lake G|Kaby Lake Graphics|l=core}})</th></tr>
 
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Kaby Lake]] [[max cpu count::1]] [[core name::Kaby Lake G]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
Line 725: Line 583:
  
 
== Documents ==
 
== Documents ==
−
=== 7th Generation ===
 
 
* [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]]
 
* [[:File:7th-gen-intel-core-january-product-brief.pdf|7th gen intel core & Intel Xeon processor briefing]]
 
* [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]]
 
* [[:File:7th Generation Intel® Core™ Processor Product Brief.pdf|7th Generation Intel Core Processor Product Brief]]
Line 734: Line 591:
 
* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]]
 
* [[:File:7th-generation-core-processor-deskop-iot-platform-brief.pdf|7th Generation Intel Core Processor-Based Platforms for Internet of Things (IoT) Solutions Platform brief]]
 
* [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]]
 
* [[:File:how-to-watch-4k-uhd-premium-content-with-your-pc.pdf|HOW TO WATCH 4K ULTRA HD (UHD) PREMIUM CONTENT WITH YOUR PC]]
−
=== 8th Generation ===
 
−
* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]]
 
−
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
 
−
* [[:File:8th-gen-radeon-rx-vega-m-product-overview.pdf|8th Gen Intel® Core processors With RadeonTM RX Vega M Graphics]]
 
  
−
== Bibliography ==
+
== References ==
 
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015
 
* Intel Developer Forum 2015, San Francisco, August 18-20, 2015
 
* Intel Technology and Manufacturing Day, March 28, 2017
 
* Intel Technology and Manufacturing Day, March 28, 2017
−
* 8th Generation core announcement, August 21, 2017
 
−
* IEEE Hot Chips 30 Symposium (HCS) 2018.
 
−
* Schor, David. (September, 2018). "''[https://fuse.wikichip.org/news/1634/hot-chips-30-intel-kaby-lake-g/ Hot Chips 30: Intel Kaby Lake G]''"
 
  
 
== Artwork ==
 
== Artwork ==
Line 761: Line 611:
 
File:7th-gen-wafer.jpg|7th gen core silicon wafers
 
File:7th-gen-wafer.jpg|7th gen core silicon wafers
 
</gallery>
 
</gallery>
 +
 +
== External Links ==
 +
* [https://www.youtube.com/watch?v=3zoD3_ZZeaw Kaby Lake – All CPUs Benchmarks ROUNDUP]
  
 
== See also ==
 
== See also ==
 
* {{amd|microarchitectures/zen|AMD's Zen}}
 
* {{amd|microarchitectures/zen|AMD's Zen}}

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Facts about "Kaby Lake - Microarchitectures - Intel"
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codenameKaby Lake +
core count2 + and 4 +
designerIntel +
first launchedAugust 30, 2016 +
full page nameintel/microarchitectures/kaby lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameKaby Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +