Editing intel/microarchitectures/ivy bridge (client)

{{intel title|Ivy Bridge|arch}}
{{microarchitecture
| atype            = CPU
| name             = Ivy Bridge
| designer         = Intel
| manufacturer     = Intel
| introduction     = May 4, 2011
| phase-out        = April, 2013
| process          = 22 nm
|isa=x86-64

| succession       = Yes
| predecessor      = Sandy Bridge
| predecessor link = intel/microarchitectures/sandy bridge
| successor        = Haswell
| successor link   = intel/microarchitectures/haswell
}}
'''Ivy Bridge''' ('''IVB''') was [[Intel]]'s  [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a [[process shrink]] of {{\\|Sandy Bridge}} which introduced a number of enhancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products.

For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v2}}, {{intel|Xeon E5|Xeon E5 v2}}, and {{intel|Xeon E7|Xeon E7 v2}}.
== Codenames ==
{{empty section}}

== Process Technology ==
{| class="wikitable" style="float: right;"
! colspan="2" | 22nm Manufacturing Fabs
|-
! Fab !! Location
|-
| D1C || Hillsboro, Oregon
|-
| D1D || Hillsboro, Oregon
|-
| Fab 32 || Chandler, Arizona
|-
| Fab 12 || Chandler, Arizona
|-
| Fab 28 || Kiryat Gat, Israel
|}
Ivy Bridge is designed to be manufactured using [[22 nm]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively.

[[Scaling]]:

{| class="wikitable"
|-
! !! Sandy Bridge !! Ivy Bridge !! Δ !! rowspan="7" | [[File:intel 22nm fin.png|250px]]
|-
| || [[32 nm]] || [[22 nm]] ||
|-
| Fin Pitch || style="text-align: center;" rowspan="3" | N/A || 60 nm || style="text-align: center;" rowspan="3" | N/A
|-
| Fin Width || 8 nm
|-
| Fin Height || 34 nm
|-
| Gate Pitch || 112.5 nm || 90 nm || 0.80x
|-
| Interconnect Pitch || 112.5 nm || 80 nm || 0.71x
|}
{{clear}}

== Architecture ==
{{empty section}}
=== Key changes from {{\\|Sandy Bridge}} ===
{{empty section}}

====New instructions ====
Ivy Bridge introduced a number of {{x86|extensions|new instructions}}:

* {{x86|F16C|<code>F16C</code>}} - Extension for performing HP-SP conversions
* {{x86|RDRAND|<code>RDRAND</code>}} - Secure Key Technology extension
* FS/GS base access

=== Block Diagram ===
==== Client SoC ====

====== Individual Core ======
[[File:ivy bridge block diagram.svg]]

== Die ==
===Quad-core Ivy Bridge die===
*Intel Core i7 3770K/i7 3770/i5 3570K
* 1,480,000,000 transistors
* 160 mm<sup>2</sup>
* 4 CPU cores
* 1 GPU core
** 2x8xEU (64 ALUs)
* [[22 nm process]]
: [[File:ivy bridge die (quad-core).jpg|850px]]

: [[File:ivy bridge die (quad-core) (annotated).png|850px]]

===Hexa-core Ivy Bridge Die===
* {{intel|Core i7-4960X}}
* 1,860,000,000 transistors
* 256.5 mm²
* 15.0 mm x 17.1 mm
* 6 CPU cores
* [[22 nm process]]

:[[File:ivy bridge (hexa-core) die shot.png|650px]]

:[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]]


===Pentadeca-Core Ivy Bridge die===

* 541 mm²
* 4,310,000,000 transistors
* [[22 nm process]]
* 15 CPU cores

[[File:intel xeon e7 v2.jpg|850px]]

== Cores ==
{{empty section}}

== All Ivy Bridge Chips ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc6 tc7 tc20 tc21 tc22 tc23 tc24 tc25">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of Ivy  Bridge Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?turbo frequency (2 cores)#GHz
 |?turbo frequency (3 cores)#GHz
 |?turbo frequency (4 cores)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=20
 |mainlabel=-
 |limit=200
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]]}}
</table>
{{comp table end}}
codename	Ivy Bridge +
designer	Intel +
first launched	May 4, 2011 +
full page name	intel/microarchitectures/ivy bridge (client) +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Ivy Bridge +
phase-out	April 2013 +
process	22 nm (0.022 μm, 2.2e-5 mm) +