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| phase-out        = April, 2013
 
| phase-out        = April, 2013
 
| process          = 22 nm
 
| process          = 22 nm
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|isa=x86-64
 
  
 
| succession      = Yes
 
| succession      = Yes
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| successor link  = intel/microarchitectures/haswell
 
| successor link  = intel/microarchitectures/haswell
 
}}
 
}}
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'''Ivy Bridge''' ('''IVB''') was [[Intel]]'s  [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a [[process shrink]] of {{\\|Sandy Bridge}} which introduced a number of enhancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products.
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'''Ivy Bridge''' ('''IVB''') was [[Intel]]'s  [[microarchitecture]] based on the [[22 nm process]] for desktops and servers. Ivy Bridge was introduced in 2011 as a [[process shrink]] of {{\\|Sandy Bridge}} which introduced a number enhancements. Ivy Bridge became Intel's first microarchitecture to use [[tri-gate transistor]]s for their commercial products.
  
 
For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v2}}, {{intel|Xeon E5|Xeon E5 v2}}, and {{intel|Xeon E7|Xeon E7 v2}}.
 
For desktop and mobile, Ivy Bridge is branded as 3rd Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v2}}, {{intel|Xeon E5|Xeon E5 v2}}, and {{intel|Xeon E7|Xeon E7 v2}}.
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== Process Technology ==
 
== Process Technology ==
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{| class="wikitable" style="float: right;"
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Ivy Bridge is designed to be manufactured using [[22 nm]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively.
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! colspan="2" | 22nm Manufacturing Fabs
 
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|-
 
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! Fab !! Location
 
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|-
 
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| D1C || Hillsboro, Oregon
 
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|-
 
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| D1D || Hillsboro, Oregon
 
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|-
 
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| Fab 32 || Chandler, Arizona
 
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|-
 
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| Fab 12 || Chandler, Arizona
 
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|-
 
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| Fab 28 || Kiryat Gat, Israel
 
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|}
 
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Ivy Bridge is designed to be manufactured using [[22 nm]] Tri-gate [[FinFET]] transistors. This is Intel's first generation of [[FinFET]]. This correlates to 8 nm Fin width and a 60 nm Fin pitch (shown below). SRAM cell is at 0.1080 µm² and 0.092 µm² for high performance and high density respectively.
 
  
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[[Scaling]]:
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Scaling:
  
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[[File:intel 14nm gate.png|215px|left]]
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
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! !! Sandy Bridge !! Ivy Bridge !! Δ !! rowspan="7" | [[File:intel 22nm fin.png|250px]]
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! !! Sandy Bridge !! Ivy Bridge !!  
 
|-
 
|-
 
| || [[32 nm]] || [[22 nm]] ||
 
| || [[32 nm]] || [[22 nm]] ||
 
|-
 
|-
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| Fin Pitch || style="text-align: center;" rowspan="3" | N/A || 60 nm || style="text-align: center;" rowspan="3" | N/A
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| Fin Pitch || - || 60 nm || N/A
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|-
 
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| Fin Width​ || 8 nm
 
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|-
 
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| Fin Height​ || 34 nm
 
 
|-
 
|-
 
| Gate Pitch || 112.5 nm || 90 nm || 0.80x
 
| Gate Pitch || 112.5 nm || 90 nm || 0.80x
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|}
 
|}
 
{{clear}}
 
{{clear}}
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== Architecture ==
 
== Architecture ==
 
{{empty section}}
 
{{empty section}}
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=== Key changes from {{\\|Sandy Bridge}} ===
 
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{{empty section}}
 
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====New instructions ====
 
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Ivy Bridge introduced a number of {{x86|extensions|new instructions}}:
 
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* {{x86|F16C|<code>F16C</code>}} - Extension for performing HP-SP conversions
 
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* {{x86|RDRAND|<code>RDRAND</code>}} - Secure Key Technology extension
 
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* FS/GS base access
 
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=== Block Diagram ===
 
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==== Client SoC ====
 
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====== Individual Core ======
 
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[[File:ivy bridge block diagram.svg]]
 
  
 
== Die ==
 
== Die ==
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===Quad-core Ivy Bridge die===
 
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*Intel Core i7 3770K/i7 3770/i5 3570K
 
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* 1,480,000,000 transistors
 
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* 160 mm<sup>2</sup>
 
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* 4 CPU cores
 
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* 1 GPU core
 
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** 2x8xEU (64 ALUs)
 
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* [[22 nm process]]
 
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: [[File:ivy bridge die (quad-core).jpg|850px]]
 
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−
: [[File:ivy bridge die (quad-core) (annotated).png|850px]]
 
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===Hexa-core Ivy Bridge Die===
 
===Hexa-core Ivy Bridge Die===
 
* {{intel|Core i7-4960X}}
 
* {{intel|Core i7-4960X}}
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* 256.5 mm²
 
* 256.5 mm²
 
* 15.0 mm x 17.1 mm
 
* 15.0 mm x 17.1 mm
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* 6 CPU cores
 
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* [[22 nm process]]
 
  
 
:[[File:ivy bridge (hexa-core) die shot.png|650px]]
 
:[[File:ivy bridge (hexa-core) die shot.png|650px]]
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:[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]]
 
:[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]]
  
 +
===Quad-core Ivy Bridge die===
 +
: [[File:ivy bridge die (quad-core).jpg|850px]]
  
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===Deca-core Ivy Bridge Die===
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: [[File:ivy bridge die (quad-core) (annotated).png|850px]]
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* 341 mm²
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* 1,480,000,000 transistors
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* 10 CPU cores
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* 160 mm<sup>2</sup>
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* [[22 nm process]]
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* 4 CPU cores
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* 1 GPU core
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:[[File:intel ivy-bridge E5-2600 v2 die shot.jpeg|650px]]
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** 2x8xEU (64 ALUs)
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===Pentadeca-Core Ivy Bridge die===
 
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* 541 mm²
 
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* 4,310,000,000 transistors
 
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* 15 CPU cores
 
 
* [[22 nm process]]
 
* [[22 nm process]]
−
 
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[[File:intel xeon e7 v2.jpg|850px]]
 
  
 
== Cores ==
 
== Cores ==
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           created and tagged accordingly.
  
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{{comp table start}}
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<table class="wikitable sortable">
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<table class="comptable sortable tc6 tc7 tc20 tc21 tc22 tc23 tc24 tc25">
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<tr><th colspan="12" style="background:#D6D6FF;">Ivy Bridge Chips</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of Ivy  Bridge Processors</th></tr>
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<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
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<tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
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{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]]
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]] [[max cpu count::1]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?microarchitecture
 +
|?platform
 +
|?core name
 
  |?first launched
 
  |?first launched
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  |?release price
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  |?sdp
−
|?microprocessor family
 
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|?core name
 
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|?core count
 
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|?thread count
 
−
|?l2$ size
 
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|?l3$ size
 
 
  |?tdp
 
  |?tdp
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  |?base frequency#GHz
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  |?base frequency
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|?turbo frequency (1 core)#GHz
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  |?max memory
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|?turbo frequency (2 cores)#GHz
 
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|?turbo frequency (3 cores)#GHz
 
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|?turbo frequency (4 cores)#GHz
 
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  |?max memory#GiB
 
 
  |?integrated gpu
 
  |?integrated gpu
 
  |?integrated gpu base frequency
 
  |?integrated gpu base frequency
 
  |?integrated gpu max frequency
 
  |?integrated gpu max frequency
 
  |format=template
 
  |format=template
−
  |template=proc table 3
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  |template=proc table 2
−
|searchlabel=
+
  |userparam=13
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
  |userparam=20
 
 
  |mainlabel=-
 
  |mainlabel=-
−
|limit=200
 
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Ivy Bridge]]}}
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<tr><th colspan="12">Count: {{#ask:[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Ivy Bridge]]|format=count}}</th></tr>
 
</table>
 
</table>
−
{{comp table end}}
 

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Facts about "Ivy Bridge - Microarchitectures - Intel"
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codenameIvy Bridge +
designerIntel +
first launchedMay 4, 2011 +
full page nameintel/microarchitectures/ivy bridge (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIvy Bridge +
phase-outApril 2013 +
process22 nm (0.022 μm, 2.2e-5 mm) +