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==== CPU changes ==== | ==== CPU changes ==== | ||
− | Haswell can | + | Haswell can execute more classes of instructions with 4 ops/cycle throughput. SandyBridge/Ivybridge could do so only for NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs). |
* MOVSX and MOVZX have 4 op/cycle throughput for 8->32, 8->64 and 16->64 bit forms. | * MOVSX and MOVZX have 4 op/cycle throughput for 8->32, 8->64 and 16->64 bit forms. | ||
− | * | + | * Some ALU operations have 4 op/cycle throughput for 32-bit registers: XOR, OR, NEG, NOT, although not all (ADD, SUB, CMP and AND don't). |
* Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles, variable SHLD/SHRD from 2 cycles to 4 cycles. | * Variable shifts and rotates (SHL r32, CL etc) latency increased from 1 cycle to 2 cycles, variable SHLD/SHRD from 2 cycles to 4 cycles. | ||
* REP MOVS copy is twice as fast: now ~52 bytes/cycle. | * REP MOVS copy is twice as fast: now ~52 bytes/cycle. | ||
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==== Front-end ==== | ==== Front-end ==== | ||
− | The front-end is the complicated part of the microarchitecture | + | The front-end is the complicated part of the microarchitecture has it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public. |
Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads. | Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads. | ||
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Client die come in [[dual-core|2]], [[quad-core|4]], or [[octa-core|8]] cores setup with dual/quad being mainstream models and the [[octa-core]] being the high-end desktop. | Client die come in [[dual-core|2]], [[quad-core|4]], or [[octa-core|8]] cores setup with dual/quad being mainstream models and the [[octa-core]] being the high-end desktop. | ||
− | ==== Dual-core | + | ====Dual-core ==== |
* 22 nm process | * 22 nm process | ||
* 960,000,000 transistors | * 960,000,000 transistors | ||
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* 2 CPU cores | * 2 CPU cores | ||
− | + | : [[File:haswell die (dual-core).jpg|850px]] | |
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− | + | ====Quad-core ==== | |
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− | ====Quad-core | ||
* [[22 nm process]] | * [[22 nm process]] | ||
* 1,400,000,000 transistors | * 1,400,000,000 transistors | ||
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: [[File:haswell die (quad-core) (annotated).png|850px]] | : [[File:haswell die (quad-core) (annotated).png|850px]] | ||
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====Octa-core ==== | ====Octa-core ==== | ||
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<tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr> | <tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr> | ||
{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}} | {{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}} | ||
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::1]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::1]] | ||
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|?full page name | |?full page name | ||
|?model number | |?model number |
Facts about "Haswell - Microarchitectures - Intel"
codename | Haswell + |
core count | 2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 + |
designer | Intel + |
first launched | June 4, 2013 + |
full page name | intel/microarchitectures/haswell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Haswell + |
phase-out | 2015 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |