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====New instructions ==== | ====New instructions ==== | ||
+ | {{main|#Added instructions|l1=See #Added_instructions for the complete list}} | ||
Haswell introduced a number of new instructions: | Haswell introduced a number of new instructions: | ||
* {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bits vectors. | * {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bits vectors. | ||
+ | ** Vector Gather supprt | ||
+ | ** Any-to-Any permutes | ||
+ | ** Vector-Vector Shifts | ||
* {{x86|BMI1|<code>BMI1</code>}} - Bit Manipulation Instructions Sets 1 | * {{x86|BMI1|<code>BMI1</code>}} - Bit Manipulation Instructions Sets 1 | ||
* {{x86|BMI2|<code>BMI2</code>}} - Bit Manipulation Instructions Sets 2 | * {{x86|BMI2|<code>BMI2</code>}} - Bit Manipulation Instructions Sets 2 | ||
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* {{x86|FMA3|<code>FMA3</code>}} - Floating Point Multiply Accumulate, 3 operands | * {{x86|FMA3|<code>FMA3</code>}} - Floating Point Multiply Accumulate, 3 operands | ||
* {{x86|TSX|<code>TSX</code>}} - Transactional Synchronization Extensions | * {{x86|TSX|<code>TSX</code>}} - Transactional Synchronization Extensions | ||
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=== Block Diagram === | === Block Diagram === |
Facts about "Haswell - Microarchitectures - Intel"
codename | Haswell + |
core count | 2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 + |
designer | Intel + |
first launched | June 4, 2013 + |
full page name | intel/microarchitectures/haswell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Haswell + |
phase-out | 2015 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |