|atype=CPU

|name=Haswell

|designer=Intel

|manufacturer=Intel

|introduction=June 4, 2013

|phase-out=2015

|process=22 nm

|cores=2

|cores 2=4

|cores 3=6

|cores 4=8

|cores 5=10

|cores 6=12

|cores 8=16

|cores 9=18

|type=Superscalar

|speculative=Yes

|renaming=Yes

|stages min=14

|stages max=19

|isa=x86-64

|extension=MOVBE

|extension 2=MMX

|extension 3=SSE

|extension 4=SSE2

|extension 5=SSE3

|extension 6=SSSE3

|extension 7=SSE4.1

|extension 8=SSE4.2

|extension 9=POPCNT

|extension 10=AVX

|extension 11=AVX2

|extension 12=AES

|extension 13=PCLMUL

|extension 14=FSGSBASE

|extension 15=RDRND

|extension 16=FMA3

|extension 17=BMI

|extension 18=BMI2

|extension 19=F16C

|extension 20=VT-x

|extension 21=VT-d

|extension 22=TXT

|extension 23=TSX

|l1i=32 KB

|l1i per=core

|l1i desc=8-way set associative

|l1d=32 KB

|l1d per=core

|l1d desc=8-way set associative

|l2=256 KB

|l2 per=core

|l2 desc=8-way set associative

|l3=2 MB

|l3 per=core

|l3 desc=1.5 MB/core on Iris Pro GPUs equipped models

|l4=128 MB

|l4 per=package

|l4 desc=on Iris Pro GPUs only

|core name=Haswell H

|core name 2=Haswell E

|core name 3=Haswell EP

|core name 4=Haswell EX

|core name 5=Haswell DT

|core name 6=Haswell MB

|core name 7=Haswell ULT

|core name 8=Haswell ULX

|predecessor=Ivy Bridge

|predecessor link=intel/microarchitectures/ivy bridge

|successor=Broadwell

|successor link=intel/microarchitectures/broadwell

While sharing a lot of similarities with its predecessor {{\\|Ivy Bridge}}, Haswell introduces many new enhancements and features. Haswell is the first desktop-line of x86s by Intel tailored for a [[system on chip]] architecture. This is a significant move that will continue to be developed over the next couple of microarchitectures. Overall Haswell shares the same basic flow as {{\\|Sandy Bridge}} and {{\\|Ivy Bridge|Ivy}} but expands on them considerably in the execution engine with wider execution units and additional scheduler ports.

* Fully Integrated Voltage Regulator (FIVR)

Haswell can do many general purpose instructions with 4 ops/cycle throughput. SandyBridge/Ivybridge could do so only for NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs).

* Many ALU operations have 4 op/cycle throughput for GP registers: XOR, OR, NEG, NOT, ADD, SUB, CMP, AND, etc.

The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With Haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle.

The front-end is the complicated part of the microarchitecture as it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public.

Continuing with the decoder is the [[register renaming]] stage. This is crucial for out-of-order execution. In this stage the architectural x86 registers get mapped into one of the many physical registers. The integer physical register file (PRF) has been enlarged by 8 addition registers for a total 168. Likewise the FP PRF was extended by 24 registers bringing it too to 168 registers. The larger increase in the FP PRF is likely to accommodate the new {{x86|AVX2}} extension. The [[reorder buffer|ROB]] in Haswell has been increased to 192 entries (from 168 in Ivy) where each entry corresponds to a single µOp. The ROB is fixed split between the two threads. Additional scheduler resources get allocated as well - this includes stores, loads, and branch buffer entries. Note that due to how dependencies are handled, there may be more or less µOps than what was fed in. For the most part, the renamer is unified and deals with both integers and vectors. Resources, however, are partitioned between the two threads. Finally, as a last step, the µOps are matched with a port depending on their intended execution purpose. Up to 4 fused µOps may be renamed and handled per thread per cycle. Both the load and store in-flight units were increased to 72 and 42 entries respectively.

Some of the biggest architectural changes were done in the area of the execution units. Haswell widened the scheduler by two ports - one new integer dispatch port and a new memory port bringing the total to 8 µOps/cycle. The various ports have also been rebalanced. The new port 6 adds another Integer ALU designs to improve integer workloads freeing up Port 0 and 1 for vector works. It also adds a second branch unit to lower the congestion for Port 0. The second port that was added, Port 7 adds a new [[address generation unit|AGU]]. This is largely due to the improvements for {{x86|AVX2}} that roughly doubled its throughput. Port 0 had its ALU/Mul/shifter extended to 256-bits; same is true for the vector ALU on port 1 and the ALU/shuffle on port 5. Additionally a 256-bit FMA unit were added to both port 0 and port 1. The change makes it possible for FMAs and FMULs to issue on both ports. In theory, Haswell can peak at over double the performance of {{\|Sandy Bridge}}, with 16 double / 32 single precision [[FLOP]]/cycle + Integer ALU option +  Vector operation.

Overclocking needs to be done on an unlocked part such as the [[Core i7-5820K]], [[Core i7-5930K]], or [[Core i7-5960X]] Extreme Edition. Additionally those chips need to be paired with the Intel X99 Chipset.

The 5930K and the 5820K are [[hexa-core]] parts whereas the [[5960X]] is an octa-core part. Between 28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]].

Haswell provides a Coarsed BCLK ratios of either 100 MHz, 125 MHz, or 167 MHz (this was consequently changed in {{intel|Skylake#Overclocking|Skylake}}). The clock is generated internally by the chipset, but motherboard ODMs could generate it independently. A single BCLK from the PCH is fed in < 1 MHz steps, however in practice the input is very much limited by PCI Express and DMI PLL interface. This works out to 100 MHz ± 5-7% PEG/DMI @ 5:5, 125 MHz ±5-7% PEG/DMI @ 5:4, and 166.66 MHz ±5-7% @ 5:3.

 

 

All the clock domains in Haswell are derived from the BCLK (also called DMICLK). In the diagram on the right '''(xC)''' refers to the Core Frequency and is represented as a multiple of BCLK (Core Frequency = BCLK × Core Freq Multiplier up to x80). Likewise '''(xM)''' refers to the memory ratio (up to 2667 MT/s in granularity operations of 200 and 266 MHz) and Two additional multipliers to adjust the PEG(PCIe & Graphics)/DMI links which should remain at a nominal frequency of 100 MHz.

Voltage control is done by Haswell's new FIVER (Full Integrated Voltage Regulator) based architecture. This means that voltage arrives via the V_CCin input from the motherboard into the processor and onto the voltage regulator (V_CCin = [[SVID]] 1.8 V Nom up to 2.3 V+). Internally, the various voltage planes are all derived from there. This includes the V_CORE, V_RING, and V_SA. With the memory voltage (V_DDQ = 1.2 V Nom) provided from the motherboard with to its own rail.

==== Dual-core GT2 ====

==== Dual-core GT3 ====

 

====Quad-core GT2 ====

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips

<table class="comptable sortable tc6 tc7 tc20 tc21 tc22 tc23 tc24 tc25">

<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of Haswell Processors</th></tr>

<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>

{{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}

<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Uniprocessors]]</th></tr>

<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Multiprocessors]] (2-way)</th></tr>

<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="20">[[Multiprocessors]] (4-way)</th></tr>

{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]] [[max cpu count::4]]

  |?first launched

  |?release price

  |?release price

  |?base frequency#GHz

  |?max memory#GiB

  |template=proc table 3

  |userparam=20

{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Haswell]]}}