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Voltage control is done by Haswell's new FIVER (Full Integrated Voltage Regulator) based architecture. This means that voltage arrives via the V<sub>CCin</sub> input from the motherboard into the processor and onto the voltage regulator (V<sub>CCin</sub> = [[SVID]] 1.8 V Nom up to 2.3 V+). Internally, the various voltage planes are all derived from there. This includes the V<sub>CORE</sub>, V<sub>RING</sub>, and V<sub>SA</sub>. With the memory voltage (V<sub>DDQ</sub> = 1.2 V Nom) provided from the motherboard with to its own rail. | Voltage control is done by Haswell's new FIVER (Full Integrated Voltage Regulator) based architecture. This means that voltage arrives via the V<sub>CCin</sub> input from the motherboard into the processor and onto the voltage regulator (V<sub>CCin</sub> = [[SVID]] 1.8 V Nom up to 2.3 V+). Internally, the various voltage planes are all derived from there. This includes the V<sub>CORE</sub>, V<sub>RING</sub>, and V<sub>SA</sub>. With the memory voltage (V<sub>DDQ</sub> = 1.2 V Nom) provided from the motherboard with to its own rail. | ||
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== Die == | == Die == |
Facts about "Haswell - Microarchitectures - Intel"
codename | Haswell + |
core count | 2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 + |
designer | Intel + |
first launched | June 4, 2013 + |
full page name | intel/microarchitectures/haswell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Haswell + |
phase-out | 2015 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |