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Latest revision Your text
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*** Per package
 
*** Per package
 
*** Only on the {{intel|Iris Pro}} GPUs
 
*** Only on the {{intel|Iris Pro}} GPUs
 
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** TLBs:
Haswell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.
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*** ITLB
 
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**** 4KB page translations:
* TLBs:
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***** 128 entries; 4-way set associative
** ITLB
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***** fixed partition; divided between the two threads
*** 4KB page translations:
+
**** 2MB/4MB page translations:
**** 128 entries; 4-way set associative
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***** 8 entries; fully associative
**** dynamic partition; divided between the two threads
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***** Duplicated for each thread
*** 2MB/4MB page translations:
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*** DTLB
**** 8 entries; fully associative
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**** 4KB page translations:
**** Duplicated for each thread
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***** 64 entries; 4-way set associative
** DTLB
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***** fixed partition; divided between the two threads
*** 4KB page translations:
+
**** 2MB/4MB page translations:
**** 64 entries; 4-way set associative
+
***** 32 entries; 4-way set associative
**** fixed partition; divided between the two threads
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**** 1G page translations:
*** 2MB/4MB page translations:
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***** 4 entries; 4-way set associative
**** 32 entries; 4-way set associative
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*** STLB
*** 1G page translations:
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**** 4KB+2M page translations:
**** 4 entries; 4-way set associative
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***** 1024 entries; 8-way set associative
** STLB
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***** shared
*** 4KB+2M page translations:
 
**** 1024 entries; 8-way set associative
 
**** shared
 
  
 
== Core ==
 
== Core ==

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codenameHaswell +
core count2 +, 4 +, 6 +, 8 + and 16 +
designerIntel +
first launchedJune 4, 2013 +
full page nameintel/microarchitectures/haswell (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameHaswell +
phase-out2015 +
pipeline stages (max)19 +
pipeline stages (min)14 +
process22 nm (0.022 μm, 2.2e-5 mm) +