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{{intel title|Haswell|arch}} | {{intel title|Haswell|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | + | | name = Haswell | |
− | |name=Haswell | + | | manufacturer = Intel |
− | + | | introduction = June 4, 2013 | |
− | |manufacturer=Intel | + | | phase-out = 2015 |
− | |introduction=June 4, 2013 | + | | process = 22 nm |
− | |phase-out=2015 | + | | cores = 2 |
− | |process=22 nm | + | | cores 2 = 4 |
− | |cores=2 | + | | cores 3 = 6 |
− | |cores 2=4 | + | | cores 4 = 8 |
− | |cores 3=6 | + | | cores 5 = 16 |
− | |cores 4=8 | + | | cores 6 = 32 |
− | |cores 5= | + | |
− | |cores 6= | + | | pipeline = Yes |
− | + | | type = Superscalar | |
− | | | + | | OoOE = Yes |
− | | | + | | speculative = Yes |
− | | | + | | renaming = Yes |
− | |speculative=Yes | + | | isa = IA-32 |
− | |renaming=Yes | + | | isa 2 = x86-64 |
− | |stages min=14 | + | | stages min = 14 |
− | |stages max=19 | + | | stages max = 19 |
− | | | + | | issues = 4 |
− | |extension=MOVBE | + | |
− | |extension 2=MMX | + | | inst = Yes |
− | |extension 3=SSE | + | | feature = |
− | |extension 4=SSE2 | + | | extension = MOVBE |
− | |extension 5=SSE3 | + | | extension 2 = MMX |
− | |extension 6=SSSE3 | + | | extension 3 = SSE |
− | |extension 7=SSE4.1 | + | | extension 4 = SSE2 |
− | |extension 8=SSE4.2 | + | | extension 5 = SSE3 |
− | |extension 9=POPCNT | + | | extension 6 = SSSE3 |
− | |extension 10=AVX | + | | extension 7 = SSE4.1 |
− | |extension 11=AVX2 | + | | extension 8 = SSE4.2 |
− | |extension 12=AES | + | | extension 9 = POPCNT |
− | |extension 13=PCLMUL | + | | extension 10 = AVX |
− | |extension 14=FSGSBASE | + | | extension 11 = AVX2 |
− | |extension 15=RDRND | + | | extension 12 = AES |
− | |extension 16= | + | | extension 13 = PCLMUL |
− | |extension 17=BMI | + | | extension 14 = FSGSBASE |
− | |extension 18=BMI2 | + | | extension 15 = RDRND |
− | |extension 19=F16C | + | | extension 16 = FMA |
− | |extension 20=VT-x | + | | extension 17 = BMI |
− | |extension 21=VT-d | + | | extension 18 = BMI2 |
− | |extension 22=TXT | + | | extension 19 = F16C |
− | |extension 23=TSX | + | | extension 20 = VT-x |
− | |l1i=32 KB | + | | extension 21 = VT-d |
− | |l1i per=core | + | | extension 22 = TXT |
− | |l1i desc=8-way set associative | + | | extension 23 = TSX |
− | |l1d=32 KB | + | |
− | |l1d per=core | + | | cache = Yes |
− | |l1d desc=8-way set associative | + | | l1i = 32 KB |
− | |l2=256 KB | + | | l1i per = core |
− | |l2 per=core | + | | l1i desc = 8-way set associative |
− | |l2 desc=8-way set associative | + | | l1d = 32 KB |
− | |l3= | + | | l1d per = core |
− | |l3 per=core | + | | l1d desc = 8-way set associative |
− | |l3 desc= | + | | l2 = 256 KB |
− | |l4=128 MB | + | | l2 per = core |
− | |l4 per=package | + | | l2 desc = 8-way set associative |
− | |l4 desc=on Iris Pro GPUs only | + | | l3 = 1.5 MB |
− | |core name=Haswell H | + | | l3 per = core |
− | |core name 2=Haswell E | + | | l3 desc = |
− | |core name 3=Haswell EP | + | | l4 = 128 MB |
− | |core name 4=Haswell EX | + | | l4 per = package |
− | |core name 5=Haswell DT | + | | l4 desc = on Iris Pro GPUs only |
− | |core name 6=Haswell MB | + | |
− | |core name 7=Haswell ULT | + | | core names = Yes |
− | |core name 8=Haswell ULX | + | | core name = Haswell H |
− | |predecessor=Ivy Bridge | + | | core name 2 = Haswell E |
− | |predecessor link=intel/microarchitectures/ivy bridge | + | | core name 3 = Haswell EP |
− | |successor=Broadwell | + | | core name 4 = Haswell EX |
− | |successor link=intel/microarchitectures/broadwell | + | | core name 5 = Haswell DT |
− | + | | core name 6 = Haswell MB | |
− | + | | core name 7 = Haswell ULT | |
− | + | | core name 8 = Haswell ULX | |
− | + | ||
− | + | | succession = Yes | |
− | + | | predecessor = Ivy Bridge | |
− | + | | predecessor link = intel/microarchitectures/ivy bridge | |
+ | | successor = Broadwell | ||
+ | | successor link = intel/microarchitectures/broadwell | ||
}} | }} | ||
− | '''Haswell''' ('''HSW''') is [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for mobile, desktops, and servers. Haswell, which was introduced in 2013, became the successor to {{\\|Ivy Bridge}}. Haswell is named after [[wikipedia:Haswell, Colorado|Haswell, Colorado]] (Originally Molalla after [[wikipedia:Molalla, Oregon|Molalla, Oregon]], it was later renamed due to the difficult pronunciation) | + | '''Haswell''' ('''HSW''') is [[Intel]]'s [[microarchitecture]] based on the [[22 nm process]] for mobile, desktops, and servers. Haswell, which was introduced in 2013, became the successor to {{\\|Ivy Bridge}}. Haswell is named after [[wikipedia:Haswell, Colorado|Haswell, Colorado]] (Originally Molalla after [[wikipedia:Molalla, Oregon|Molalla, Oregon]], it was later renamed due to the difficult pronunciation). |
− | |||
== Codenames == | == Codenames == | ||
{| class="wikitable" | {| class="wikitable" | ||
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| Haswell E || HSW-E || High-End Desktops (HEDT) | | Haswell E || HSW-E || High-End Desktops (HEDT) | ||
|} | |} | ||
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== Architecture == | == Architecture == | ||
− | While sharing a lot of similarities with its predecessor {{\\|Ivy Bridge}}, Haswell introduces many new enhancements and features. Haswell is the first desktop-line of x86s by Intel tailored for a [[system on chip]] architecture. This is a significant move | + | While sharing a lot of similarities with its predecessor {{\\|Ivy Bridge}}, Haswell introduces many new enhancements and features. Haswell is the first desktop-line of x86s by Intel tailored for a [[system on chip]] architecture. This is a significant move since not every market segment has the same demands - high end desktops have a higher end GPU while servers don't even require one. |
=== Key changes from {{\\|Ivy Bridge}} === | === Key changes from {{\\|Ivy Bridge}} === | ||
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* Platform Controller Hub (PCH) | * Platform Controller Hub (PCH) | ||
** Shrink from [[65 nm]] to [[32 nm]] | ** Shrink from [[65 nm]] to [[32 nm]] | ||
* Support for DDR4 (server/enthusiast segments) | * Support for DDR4 (server/enthusiast segments) | ||
− | * | + | * Integrated voltage regulator (IVR) |
* New C6 & C7 sleep states | * New C6 & C7 sleep states | ||
* Cache | * Cache | ||
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** STLB been made to support 2MB pages | ** STLB been made to support 2MB pages | ||
*** Table has been doubled to 1,024 entries 8-Way (up from 512, 4-way) | *** Table has been doubled to 1,024 entries 8-Way (up from 512, 4-way) | ||
− | |||
* Scheduler has been widened, (see [[#Front-end]]) | * Scheduler has been widened, (see [[#Front-end]]) | ||
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** 2 additional execution ports (see [[#Execution_Units]]) | ** 2 additional execution ports (see [[#Execution_Units]]) | ||
* New memory model for {{x86|TSX|Transactional Synchronization Extensions}} | * New memory model for {{x86|TSX|Transactional Synchronization Extensions}} | ||
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==== GPU changes ==== | ==== GPU changes ==== | ||
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====New instructions ==== | ====New instructions ==== | ||
+ | {{main|#add instructions|l1=See #add_instructions for the complete list}} | ||
Haswell introduced a number of new instructions: | Haswell introduced a number of new instructions: | ||
* {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bits vectors. | * {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bits vectors. | ||
+ | ** Vector Gather supprt | ||
+ | ** Any-to-Any permutes | ||
+ | ** Vector-Vector Shifts | ||
* {{x86|BMI1|<code>BMI1</code>}} - Bit Manipulation Instructions Sets 1 | * {{x86|BMI1|<code>BMI1</code>}} - Bit Manipulation Instructions Sets 1 | ||
* {{x86|BMI2|<code>BMI2</code>}} - Bit Manipulation Instructions Sets 2 | * {{x86|BMI2|<code>BMI2</code>}} - Bit Manipulation Instructions Sets 2 | ||
* {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction | * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction | ||
− | * {{x86| | + | * {{x86|FMA|<code>FMA</code>}} - Floating Point Multiply Accumulate |
* {{x86|TSX|<code>TSX</code>}} - Transactional Synchronization Extensions | * {{x86|TSX|<code>TSX</code>}} - Transactional Synchronization Extensions | ||
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=== Block Diagram === | === Block Diagram === | ||
+ | Due to the success of the front end in {{\\|Ivy Bridge}}, very few changes were done in Haswell. | ||
− | |||
[[File:haswell block diagram.svg]] | [[File:haswell block diagram.svg]] | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
− | The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With | + | The memory hierarchy in Haswell had a number of changes from its predecessor. The cache bandwidth for both load and store have been doubled (64B/cycle for load and 32B/cycle for store; up from 32/16 respectively). Significant enhancements have been done to support the new gather instructions and transactional memory. With haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle. |
* Cache | * Cache | ||
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*** 32 KB 8-way [[set associative]] | *** 32 KB 8-way [[set associative]] | ||
**** 64 B line size | **** 64 B line size | ||
− | |||
**** shared by the two threads, per core | **** shared by the two threads, per core | ||
** L1D Cache: | ** L1D Cache: | ||
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**** 64 Bytes/cycle load bandwidth | **** 64 Bytes/cycle load bandwidth | ||
**** 32 Bytes/cycle store bandwidth | **** 32 Bytes/cycle store bandwidth | ||
− | |||
** L2 Cache: | ** L2 Cache: | ||
*** unified, 256 KB 8-way set associative | *** unified, 256 KB 8-way set associative | ||
*** 11 cycles for fastest load-to-use | *** 11 cycles for fastest load-to-use | ||
*** 64B/cycle bandwidth to L1$ | *** 64B/cycle bandwidth to L1$ | ||
− | |||
** L3 Cache: | ** L3 Cache: | ||
− | *** 1.5 | + | *** 1.5 MB |
− | |||
*** Per core | *** Per core | ||
** L4 Cache: | ** L4 Cache: | ||
*** 128 MB | *** 128 MB | ||
*** Per package | *** Per package | ||
− | *** Only on the {{ | + | *** Only on the {{inte|Iris Pro}} GPUs |
+ | ** TLBs: | ||
+ | *** ITLB | ||
+ | **** 4KB page translations: | ||
+ | ***** 128 entries; 4-way associative | ||
+ | ***** fixed partition; divided between the two threads | ||
+ | **** 2MB/4MB page translations: | ||
+ | ***** 8 entries; fully associative | ||
+ | ***** Duplicated for each thread | ||
+ | *** DTLB | ||
+ | **** 4KB page translations: | ||
+ | ***** 64 entries; 4-way associative | ||
+ | ***** fixed partition; divided between the two threads | ||
+ | **** 2MB/4MB page translations: | ||
+ | ***** 32 entries; 4-way associative | ||
+ | **** 1G page translations: | ||
+ | ***** 4 entries; 4-way associative | ||
+ | *** STLB | ||
+ | **** 4KB+2M page translations: | ||
+ | ***** 1024 entries; 8-way associative | ||
+ | ***** shared | ||
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=== Pipeline === | === Pipeline === | ||
Haswell, like its predecessor Ivy Bridge, also has a dual-threaded and out-of-order pipeline. | Haswell, like its predecessor Ivy Bridge, also has a dual-threaded and out-of-order pipeline. | ||
==== Front-end ==== | ==== Front-end ==== | ||
− | The front-end is the complicated part of the microarchitecture | + | The front-end is the complicated part of the microarchitecture has it deals with variable length x86 instructions ranging from 1 to 15 bytes. The main goal here is to fetch and decode correctly the next set of instructions. The caches have not changed in Haswell from {{\\|Ivy Bridge}}, with the [[L1i$]] still 32KB , 8-way set associative shared dynamically by the two threads. Instruction cache instruction fetching remains 16B/cycle. [[TLB]] is also still 128-entries, 4-way for 4KB pages and 8-entries, [[fully associative]] for 2MB page mode. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread. Haswell continued to improve the branch misses although the exact details have not been made public. |
Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads. | Haswell has the same µOps cache as Ivy Bridge - 1,536 entries organized in 32 sets of 8 cache lines with 6 µOps each. Hits can yield up to 4-µOps/cycle. The cache supports microcoded instructions (being pointers to ROM entries). Cache is shared by the two threads. | ||
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==== Execution engine ==== | ==== Execution engine ==== | ||
− | Continuing with the decoder is the [[register renaming]] stage. This is crucial for out-of-order execution. In this stage the architectural x86 registers get mapped into one of the many physical registers. The integer physical register file (PRF) has been enlarged by 8 addition registers for a total 168. Likewise the FP PRF was extended by 24 registers bringing it too to 168 registers. The larger increase in the FP PRF is likely to accommodate the new {{x86|AVX2}} extension. The [[reorder buffer|ROB]] in Haswell has been increased to 192 entries (from 168 in Ivy) where each entry corresponds to a single µOp. The | + | Continuing with the decoder is the [[register renaming]] stage. This is crucial for out-of-order execution. In this stage the architectural x86 registers get mapped into one of the many physical registers. The integer physical register file (PRF) has been enlarged by 8 addition registers for a total 168. Likewise the FP PRF was extended by 24 registers bringing it too to 168 registers. The larger increase in the FP PRF is likely to accommodate the new {{x86|AVX2}} extension. The [[reorder buffer|ROB]] in Haswell has been increased to 192 entries (from 168 in Ivy) where each entry corresponds to a single µOp. The ROD is fixed split between the two threads. Additional scheduler resources get allocated as well - this includes stores, loads, and branch buffer entries. Note that due to how dependencies are handled, there may be more or less µOps than what was fed in. For the most part, the renamer is unified and deals with both integers and vectors. Resources, however, are partitioned between the two threads. Finally, as a last step, the µOps are matched with a port depending on their intended execution purpose. Up to 4 fused µOps may be renamed and handled per thread per cycle. Both the load and store in-flight units were increased to 72 and 42 entries respectively. |
Haswell continues to use a unified scheduler for all µOps which holds 60 entries. µOps at this stage sit idle until they are cleared to be executed via their assigned dispatch port. µOps may be held due to resource unavailability. | Haswell continues to use a unified scheduler for all µOps which holds 60 entries. µOps at this stage sit idle until they are cleared to be executed via their assigned dispatch port. µOps may be held due to resource unavailability. | ||
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===== Execution Units ===== | ===== Execution Units ===== | ||
− | Some of the biggest architectural changes were done in the area of the execution units. Haswell widened the scheduler by two ports - one new integer dispatch port and a new memory port bringing the total to 8 µOps/cycle. The various ports have also been rebalanced. The new port 6 adds another Integer ALU designs to improve integer workloads freeing up Port 0 and 1 for vector works. It also adds a second branch unit to | + | Some of the biggest architectural changes were done in the area of the execution units. Haswell widened the scheduler by two ports - one new integer dispatch port and a new memory port bringing the total to 8 µOps/cycle. The various ports have also been rebalanced. The new port 6 adds another Integer ALU designs to improve integer workloads freeing up Port 0 and 1 for vector works. It also adds a second branch unit to low the congestion Port 0. The second port that was added, Port 7 adds a new [[address generation unit|AGU]]. This is largely due to the improvements for {{x86|AVX2}} that roughly doubled its throughput. Port 0 had its ALU/Mul/shifter extended to 256-bits; same is true for the vector ALU on port 1 and the ALU/shuffle on port 5. Additionally a 256-bit FMA unit were added to both port 0 and port 1. The change makes it possible for FMAs and FMULs to issue on both ports. In theory, Haswell can peak at over double the performance of {{\|Sandy Bridge}}, with 16 double / 32 single precision [[FLOP]]/cycle + Integer ALU option + Vector operation. |
The scheduler dispatches up to 8 ready µOps/cycle in [[FIFO]] order through the dispatch ports. µOps involving computational operations are sent to ports 0, 1, 5, and 6 to the appropriate unit. Likewise ports 2, 3, 4 and 7 are used for load/store and address calculations. | The scheduler dispatches up to 8 ready µOps/cycle in [[FIFO]] order through the dispatch ports. µOps involving computational operations are sent to ports 0, 1, 5, and 6 to the appropriate unit. Likewise ports 2, 3, 4 and 7 are used for load/store and address calculations. | ||
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Facts about "Haswell - Microarchitectures - Intel"
codename | Haswell + |
core count | 2 +, 4 +, 6 +, 8 +, 16 +, 10 +, 12 +, 14 + and 18 + |
designer | Intel + |
first launched | June 4, 2013 + |
full page name | intel/microarchitectures/haswell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Haswell + |
phase-out | 2015 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |