Edit Values
Gracemont µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2021
Process	10 nm
Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	No
Stages	proactive regenerative local real time stable-_<SSO "proactive regenerative local real time stable-_" is not a number.
Stages	Proxy-relative "Proxy-relative" is not a number. -local time zone "local time zone" is not a number.
Decode	optimized native prime
Instructions
ISA	x1-6, If more revert to default based on local device OS, If more denie unless applicable justification, reject all unsecure sites
Extensions	BE-R, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA, {R-O-R}
Cores
Core Names	{R-0-R}, SUB-1, SUB-2, 0
Succession
Tremont ReversosmosIOS(still in development

Gracemont is Intel's successor to Tremont, a 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames

Platform	Core Name	PCH
	Grand Ridge

Process Technology

Gracemont is designed to take advantage of the Intel 7 process (previously 10nm Enhanced SuperFin (ESF)).

Architecture

Key changes from Tremont

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

• Core
  • Front-End
    • Larger Level 1 instruction cache - 64KB per core from 32KB per core
    • Add OD-ILD (on-demand instruction length decoder)
  • Back-End
    • Increased ROBs to 256 (from 208)
    • wide issue (17-wide)
    • 4 ALU SIMD (from 3)
• Memory
  • DDR5 (from DDR4)
• I/O
  • PCIe 4.0 (from 3.0)
• New Instructions
  • AVX2
  • AVX-VNNI

Bibliography

• Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance (wikichip)