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| − | {{intel title|Goldmont Plus|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Goldmont Plus
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |introduction=December 11, 2017
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| − | |process=14 nm
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| − | |cores=2
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| − | |cores 2=4
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| − | |type=Superscalar
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |isa=x86-64
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| − | |extension=MOVBE
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| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4.1
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| − | |extension 8=SSE4.2
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| − | |extension 9=POPCNT
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| − | |extension 10=AES
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| − | |extension 11=PCLMUL
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| − | |extension 12=RDRND
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| − | |extension 13=XSAVE
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| − | |extension 14=XSAVEOPT
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| − | |extension 15=FSGSBASE
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| − | |extension 16=PTWRITE
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| − | |extension 17=RDPID
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| − | |extension 18=SGX
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| − | |extension 19=UMIP
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| − | |extension 20=SHA
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| − | |l1i=32 KiB
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| − | |l1i per=Core
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| − | |l1i desc=8-way set associative
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| − | |l1d=24 KiB
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| − | |l1d per=Core
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| − | |l1d desc=6-way set associative
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| − | |l2=4 MiB
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| − | |l2 per=4 Cores
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| − | |l2 desc=16-way set associative
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| − | |core name=Gemini Lake
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| − | |core name 2=Gemini Lake Refresh
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| − | |predecessor=Goldmont
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| − | |predecessor link=intel/microarchitectures/goldmont
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| − | |successor=Tremont
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| − | |successor link=intel/microarchitectures/tremont
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| − | }}
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| − | '''Goldmont Plus''' ('''GLM+''', '''GLP''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium Silver}}, and {{intel|Celeron}} families.
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| | | | |
| − | == Codenames ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Core !! Abbrev !! Target
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| − | |-
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| − | | {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices
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| − | |-
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| − | | {{intel|Gemini Lake Refresh}} || GLK || Low-power PCs, tablets, and embedded devices
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| − | |}
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| − |
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| − | == Brands ==
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| − | Intel released Goldmont Plus under 2 main brand families:
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| − |
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| − | {| class="wikitable tc4 tc5 tc6 tc7 tc8"
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| − | |-
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| − | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
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| − | |-
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| − | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AES}} !! {{x86|SHA}} !! {{x86|AVX}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
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| − | |-
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| − | | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[2 cores|2]]-[[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
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| − | |-
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| − | | rowspan="2" | [[File:intel pentium silver logo (2017).png|50px|link=intel/pentium_silver]] || rowspan="2" | {{intel|Pentium Silver}} || style="text-align: left;" | Budget || rowspan="2" | [[4 cores|4]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}}
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| − | |}
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| − |
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| − | == Release Dates ==
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| − | Goldmont Plus processors were launched on December 11, 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.
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| − |
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| − | == Technology ==
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| − | Goldmont Plus, like its predecessor, is manufactured on Intel's original [[14 nm process]] (as opposed to 14nm+ or 14nm++).
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| − |
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| − | == Compiler support ==
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| − | {{future information}}
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| − | {| class="wikitable"
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| − | |-
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| − | ! Compiler !! Arch-Specific || Arch-Favorable
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| − | |-
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| − | | [[ICC]] || <code>-march=goldmont</code> || <code>-mtune=goldmont</code>
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| − | |-
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| − | | [[GCC]] || <code>-march=goldmont</code> || <code>-mtune=goldmont</code>
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| − | |-
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| − | | [[LLVM]] || <code>-march=goldmont</code> || <code>-mtune=goldmont</code>
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| − | |-
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| − | | [[Visual Studio]] || <code>?</code> || <code>?</code>
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| − | |}
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| − |
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| − | === CPUID ===
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| − | {| class="wikitable tc1 tc2 tc3 tc4"
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| − | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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| − | |-
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| − | | rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || 0x6 || 0x7 || 0xA
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| − | |-
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| − | | colspan="4" | Family 6 Model 122
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| − | |}
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| − |
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| − | == Architecture ==
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| − | Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.
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| − | === Key changes from {{\\|Goldmont}} ===
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| − | * Core
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| − | ** Front End
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| − | *** Enhanced branch prediction
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| − | ** Back End
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| − | *** 4-way allocation (from 3)
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| − | *** 4-way retire (from 3)
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| − | ** Larger reservation station
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| − | ** Larger ROB
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| − | ** Execution Units
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| − | *** POPF latency reduced from ~80 to ~40 cycles
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| − | *** Vector divisions and square roots are faster
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| − | *** AES operations: latency reduced from 6 to 4 cycles, throughput increased to 1 op/cycle
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| − | *** SHL, SHR, SAR, ROL and ROR with counter in CL: latency reduced from 2 to 1
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| − | ** Wider integer execution unit
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| − | ** New dedicated JEU port
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| − | *** Supports faster branch redirection.
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| − | ** Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides
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| − | ** Improved {{x86|AES}} instruction latency and throughput.
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| − | ** Memory Subsystem
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| − | *** 64 KiB 2nd level pre-decode cache (from 16 KiB)
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| − | *** Larger load buffer
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| − | *** Larger store buffer
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| − | *** Improved store-to-load forwarding latency store data from register
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| − | *** New STLB
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| − | **** Shared by instruction and data
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| − | *** Paging Cache Enhancements (PxE/ePxE caches)
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| − | * Cache
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| − | ** 4 MiB L2 per quad core module (Up from 1 MiB per duplex)
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| − | * Graphics
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| − | ** {{intel|Gen 9.5|l=arch}} execution engines, {{intel|Gen 10|l=arch}} Display
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| − | * New Integration
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| − | ** {{intel|CNVi|Integrated Connectivity CNVi}}
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| − | *** Supports up to Wireless-AC CRFs
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| − | ** HDMI 2.0 (from 1.4a)
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| − | *** 2160p (4K) @ 60 Hz (from 24 Hz)
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| − | ** VP9 10-bit Profile2 hardware decoding
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| − | ** HD Graphics 50x '''→''' UHD Graphics 60x
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| − | *** {{intel|HD Graphics 505}} '''→''' {{intel|UHD Graphics 605}} (Pentium Silver J/N 5xxx with 18EU)
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| − | *** {{intel|HD Graphics 500}} '''→''' {{intel|UHD Graphics 600}} (Celeron J/N 4xxx with 12EU)
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| − |
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| − | ====New instructions ====
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| − | Goldmont Plus introduced a number of {{x86|extensions|new instructions}}:
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| − |
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| − | * {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1
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| − | * {{x86|UMIP|<code>UMIP</code>}} - User-mode instruction prevention
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| − | * {{x86|PTWRITE|<code>PTWRITE</code>}} - Trace logger write user data
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| − | * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
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| − |
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| − | === Block Diagram ===
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| − | {{empty section}}
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| − | === Memory Hierarchy ===
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| − | * Cache
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| − | ** Hardware prefetchers
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| − | ** L1 Cache:
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| − | *** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
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| − | *** 24 KiB 6-way set associative data, 64 B line size
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| − | *** Per core
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| − | ** L2 Cache:
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| − | *** 2 MiB 16-way set associative, 64 B line size
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| − | *** Per 2 cores
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| − | *** 32B/cycle, 19 cycle latency
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| − | ** L3 Cache:
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| − | *** No level 3 cache
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| − | ** RAM
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| − | *** Maximum of 1 [[GiB]], 2 GiB, 4 GiB, 8 GiB
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| − | *** dual 32-bit channels, 1 or 2 ranks per channel
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| − |
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| − | === Multithreading ===
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| − | Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology.
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| − |
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| − | == New Integration ==
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| − | === Integrated Connectivity (CNVi) ===
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| − | {{main|intel/cnvi|l1=CNVi}}
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| − | A new integration to Goldmont Plus is '''Integrated Connectivity''' ('''CNVi''') which is an architecture for wireless connectivity devices. CNVi attempts to simplify vendors bill of material (BOM) size and cost by integrating the majority of the expensive functionality found in an RF chip. The only thing not integrated are the actual analog and RF functions which come from a relatively inexpensive companion RF (CRF) module connected via a standard [[M.2]] card and provides support for things such as [[IEEE 802.11ac]].
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| − |
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| − | == All Goldmont Plus Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc5 tc6 tc7">
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| − | {{comp table header|main|12:List of Goldmont Plus-based Processors}}
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| − | {{comp table header|main|9:Main processor|3:GPU}}
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| − | {{comp table header|cols|Family|Price|Launched|Cores|%L2$|%TDP|%SDP|%Base|%Turbo|Name|%Base|%Turbo}}
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| − | {{comp table header|lsep|12:Desktop}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Goldmont Plus]] [[market segment::Desktop]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?l2$ size
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| − | |?tdp
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| − | |?sdp
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| − | |?base frequency
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| − | |?turbo frequency (1 core)#MHz
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?integrated gpu max frequency
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=14
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table header|lsep|12:Mobile}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Goldmont Plus]] [[market segment::Mobile]]
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| − | |?full page name
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| − | |?model number
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| − | |?microprocessor family
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| − | |?release price
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| − | |?first launched
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| − | |?core count
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| − | |?l2$ size
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| − | |?tdp
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| − | |?sdp
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| − | |?base frequency
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| − | |?turbo frequency (1 core)#MHz
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?integrated gpu max frequency
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=14
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]][[microarchitecture::Goldmont Plus]]}}
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| − | </table>
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| − | {{comp table end}}
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