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{{intel title|Gen9.5|arch}}
+
{{intel title|Gen9.5 LP|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
| atype            = GPU
 
| atype            = GPU
−
| name            = Gen9.5
+
| name            = Gen9.5 LP
 
| designer        = Intel
 
| designer        = Intel
 
| manufacturer    = Intel
 
| manufacturer    = Intel
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| succession      = Yes
 
| succession      = Yes
−
| predecessor      = Gen9
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| predecessor      = Gen9 LP
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| predecessor link = intel/microarchitectures/gen9
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| predecessor link = intel/microarchitectures/gen9_lp
−
| successor        = Gen10
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| successor        = Gen10 LP
−
| successor link  = intel/microarchitectures/gen10
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| successor link  = intel/microarchitectures/gen10_lp
 
}}
 
}}
−
'''Gen9.5''' (''Generation 9.5'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Kaby Lake}}-based, {{\\|Coffee Lake}}-based, {{\\|Comet Lake}}-based,and {{\\|Goldmont Plus}}-based microprocessors. Gen9.5 is the successor to {{\\|Gen9}} used by {{\\|Skylake}} and introduces a number of light enhancements.
+
'''Gen9.5 LP''' (''Generation 9.5 Low Power'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Kaby Lake}}-based microprocessors. Gen9.5 LP is the successor to {{\\|Gen9 LP}} used by {{\\|Skylake}} and introduces a number of light enhancements.
  
 
== Codenames ==
 
== Codenames ==
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{| class="wikitable tc2 tc3"
 
{| class="wikitable tc2 tc3"
 
|-
 
|-
−
! colspan="5" | Gen9.5 [[IGP]] Models !! colspan="9" | Standards
+
! colspan="5" | Gen9.5 LP [[IGP]] Models !! colspan="9" | Standards
 
|-
 
|-
 
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
 
! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !!  rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]]
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
−
| {{intel|UHD Graphics 600}} || 12 || GT1 || {{intel|Gemini Lake|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.1''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" rowspan="11" | '''2.0'''
+
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || - || rowspan="7" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="7" style="text-align: center;" | '''12''' || rowspan="7" style="text-align: center;" | '''N/A''' || rowspan="7" style="text-align: center;" | '''5.1''' || rowspan="7" style="text-align: center;" | '''4.4''' || rowspan="7" style="text-align: center;" | '''4.5''' || rowspan="7" style="text-align: center;"  colspan="2" | '''2.0'''
−
|-
 
−
| {{intel|UHD Graphics 605}} || 18 || GT1.5 || {{intel|Gemini Lake|l=core}} || -
 
−
|-
 
−
| {{intel|HD Graphics 610}} || 12 || GT1 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake U|U}} || -
 
 
|-
 
|-
 
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
 
| {{intel|HD Graphics 615}} || 24 || GT2|| {{intel|Kaby Lake Y|Y}} || -
 
|-
 
|-
 
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
 
| {{intel|HD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
−
|-
 
−
| {{intel|UHD Graphics 620}} || 24 || GT2 || {{intel|Kaby Lake U|U}} || -
 
 
|-
 
|-
 
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
 
| {{intel|HD Graphics 630}} || 24 || GT2 || {{intel|Kaby Lake S|S}}, {{intel|Kaby Lake H|H}} || -
−
|-
 
−
| {{intel|UHD Graphics 630}} || 23/24 || GT2 || {{intel|Coffee Lake S|S}} || -
 
 
|-
 
|-
 
| {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || -
 
| {{intel|HD Graphics P630}} || 24 || GT2 || {{intel|Kaby Lake H|H}} || -
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|-
 
|-
 
| {{intel|HD Graphics 620}} || KBL-U 2+2 || H0 || C0/B0 || 0x5916 || 0x2
 
| {{intel|HD Graphics 620}} || KBL-U 2+2 || H0 || C0/B0 || 0x5916 || 0x2
−
|-
 
−
| {{intel|UHD Graphics 620}} || || || || 0x5917 ||
 
 
|-
 
|-
 
| rowspan="2" | {{intel|HD Graphics 630}} || KBL-S 4+2 || B0 || F0/C0  || 0x5912 || 0x4
 
| rowspan="2" | {{intel|HD Graphics 630}} || KBL-S 4+2 || B0 || F0/C0  || 0x5912 || 0x4
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| KBL Halo 4+2 ||  ||  || 0x591B ||  
 
| KBL Halo 4+2 ||  ||  || 0x591B ||  
 
|-
 
|-
−
| rowspan="2" | {{intel|UHD Graphics 630}} || CFL-S 4+2 || rowspan="2" | 23/24 || U0 ||  || 0x3E91 ||
+
| {{intel|HD Graphics P630}} || KBL WKS 4+2 ||  ||  || 0x591D ||   
−
|-
 
−
| CFL-S 6+2 || U0 ||  || 0x3E92 ||
 
−
|-
 
−
| {{intel|HD Graphics P630}} || KBL WKS 4+2 || 24 ||  ||  || 0x591D ||   
 
 
|-
 
|-
 
| {{intel|Iris Plus Graphics 640}} || KBL-U 2+3 || rowspan="2" | 48 ||  J1 || D1/B1 || 0x5926 || 0x6
 
| {{intel|Iris Plus Graphics 640}} || KBL-U 2+3 || rowspan="2" | 48 ||  J1 || D1/B1 || 0x5926 || 0x6
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<references group=devID />
 
<references group=devID />
−
 
−
== Performance ==
 
−
<div style="overflow-x: auto;">
 
−
{| class="wikitable" style="text-align: center; white-space: nowrap;"
 
−
! rowspan="2" | Frequency !! colspan="12" | Peak Performance
 
−
|-
 
−
! rowspan="13" | &nbsp; || colspan="3" | Half Precision || rowspan="13" | &nbsp; || colspan="3" | Single Precision || rowspan="13" | &nbsp; || colspan="3" | Double Precision
 
−
|-
 
−
| Models || {{intel|HD Graphics 610|610}} || {{intel|HD Graphics 615|615}}, {{intel|HD Graphics 620|620}}, {{intel|HD Graphics 630|630}}, {{intel|HD Graphics P630|P630}} || {{intel|Iris Plus Graphics 640|640}}, {{intel|Iris Plus Graphics 650|650}} || {{intel|HD Graphics 610|610}} || {{intel|HD Graphics 615|615}}, {{intel|HD Graphics 620|620}}, {{intel|HD Graphics 630|630}}, {{intel|HD Graphics P630|P630}} || {{intel|Iris Plus Graphics 640|640}}, {{intel|Iris Plus Graphics 650|650}} || {{intel|HD Graphics 610|610}} || {{intel|HD Graphics 615|615}}, {{intel|HD Graphics 620|620}}, {{intel|HD Graphics 630|630}}, {{intel|HD Graphics P630|P630}} || {{intel|Iris Plus Graphics 640|640}}, {{intel|Iris Plus Graphics 650|650}}
 
−
|-
 
−
| Tiers || GT1 || GT2 || GT3e || GT1 || GT2 || GT3e ||  GT1 || GT2 || GT3e
 
−
|-
 
−
| Ref (FLOP/clk) || 384/cycle || 768/cycle || 1536/cycle || 192/cycle || 384/cycle || 768/cycle || 48/cycle || 96/cycle || 192/cycle
 
−
|-
 
−
| Base (300 MHz) || {{#expr: 384*.3}} [[GFLOPS]] || {{#expr: 768*.3}} GFLOPS || {{#expr: 1536*.3}} GFLOPS || {{#expr: 192*.3}} GFLOPS || {{#expr: 384*.3}} GFLOPS || {{#expr: 768*.3}} GFLOPS || {{#expr: 48*.3}} GFLOPS || {{#expr: 96*.3}} GFLOPS || {{#expr: 129*.3}} GFLOPS
 
−
|-
 
−
| Base (350 MHz) || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 1536*.35}} GFLOPS || {{#expr: 192*.35}} GFLOPS || {{#expr: 384*.35}} GFLOPS || {{#expr: 768*.35}} GFLOPS || {{#expr: 48*.35}} GFLOPS || {{#expr: 96*.35}} GFLOPS || {{#expr: 129*.35}} GFLOPS
 
−
|-
 
−
| Boost (850 MHz) || {{#expr: 384*.850}} GFLOPS || {{#expr: 768*.850}} GFLOPS || {{formatnum:{{#expr: 1536*.850}}}} GFLOPS || {{#expr: 192*.850}} GFLOPS || {{#expr: 384*.850}} GFLOPS || {{#expr: 768*.850}} GFLOPS || {{#expr: 48*.850}} GFLOPS || {{#expr: 96*.850}} GFLOPS || {{#expr: 129*.850}} GFLOPS
 
−
|-
 
−
| Boost (900 MHz) || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{formatnum:{{#expr: 1536*.9}}}} GFLOPS || {{#expr: 192*.9}} GFLOPS || {{#expr: 384*.9}} GFLOPS || {{#expr: 768*.9}} GFLOPS || {{#expr: 48*.9}} GFLOPS || {{#expr: 96*.9}} GFLOPS || {{#expr: 129*.9}} GFLOPS
 
−
|-
 
−
| Boost (950 MHz) || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{formatnum:{{#expr: 1536*.95}}}} GFLOPS || {{#expr: 192*.95}} GFLOPS || {{#expr: 384*.95}} GFLOPS || {{#expr: 768*.95}} GFLOPS || {{#expr: 48*.95}} GFLOPS || {{#expr: 96*.95}} GFLOPS || {{#expr: 129*.95}} GFLOPS
 
−
|-
 
−
| Boost (1,000 MHz) || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{formatnum:{{#expr: 1536*1}}}} GFLOPS || {{#expr: 192*1}} GFLOPS || {{#expr: 384*1}} GFLOPS || {{#expr: 768*1}} GFLOPS || {{#expr: 48*1}} GFLOPS || {{#expr: 96*1}} GFLOPS || {{#expr: 129*1}} GFLOPS
 
−
|-
 
−
| Boost (1,050 MHz) || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{formatnum:{{#expr: 1536*1.05}}}} GFLOPS || {{#expr: 192*1.05}} GFLOPS || {{#expr: 384*1.05}} GFLOPS || {{#expr: 768*1.05}} GFLOPS || {{#expr: 48*1.05}} GFLOPS || {{#expr: 96*1.05}} GFLOPS || {{#expr: 129*1.05}} GFLOPS
 
−
|-
 
−
| Boost (1,100 MHz) || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{formatnum:{{#expr: 1536*1.1}}}} GFLOPS || {{#expr: 192*1.1}} GFLOPS || {{#expr: 384*1.1}} GFLOPS || {{#expr: 768*1.1}} GFLOPS || {{#expr: 48*1.1}} GFLOPS || {{#expr: 96*1.1}} GFLOPS || {{#expr: 129*1.1}} GFLOPS
 
−
|-
 
−
| Boost (1,150 MHz) || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{formatnum:{{#expr: 1536*1.15}}}} GFLOPS || {{#expr: 192*1.15}} GFLOPS || {{#expr: 384*1.15}} GFLOPS || {{#expr: 768*1.15}} GFLOPS || {{#expr: 48*1.15}} GFLOPS || {{#expr: 96*1.15}} GFLOPS || {{#expr: 129*1.15}} GFLOPS
 
−
|}
 
−
</div>
 
  
 
== Hardware Accelerated Video ==
 
== Hardware Accelerated Video ==
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== Process Technology ==
 
== Process Technology ==
 
{{main|intel/microarchitectures/kaby lake#Process_Technology|l1=Kaby Lake § Process Technology}}
 
{{main|intel/microarchitectures/kaby lake#Process_Technology|l1=Kaby Lake § Process Technology}}
−
Gen9.5 are part of the Kaby Lake SoC die which uses an enhanced [[14 nm process|14nm+ process]].
+
Gen9 .5LP are part of the Kaby Lake SoC die which uses an enhanced [[14 nm process|14nm+ process]].
  
 
== Architecture ==
 
== Architecture ==
−
Gen9.5 is very similar to {{\\|Gen9}} with a number of enhancements.
+
Gen9.5 LP is very similar to {{\\|Gen9 LP}} with a number of enhancements.
  
−
=== Key changes from {{\\|Gen9}} ===
+
=== Key changes from {{\\|Gen9 LP}} ===
−
* Enhanced "14nm+" process (while CPU cores base frequency was increased, GPU speed remains unchanged)
+
* Enhanced "14nm+" process (while CPU cores base frequency was increase, GPU speed remains unchanged)
−
** Power consumption is reduced
 
 
* Display block
 
* Display block
−
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3)
+
** [[Embedded DisplayPort]] ([[eDP]]) now supports eDP Standard 1.4 (From 1.3 in Skylake)
 
* Unslice
 
* Unslice
 
** New native hardware support for 4K HEVC/VP9
 
** New native hardware support for 4K HEVC/VP9
−
** WiDi (Miracast) support has been enhanced
 
−
** VQE wider color gamma
 
 
* DRM
 
* DRM
 
** Support for Microsoft's PlayReady 3.0
 
** Support for Microsoft's PlayReady 3.0
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[[File:kaby lake soc block diagram.svg|900px]]
 
[[File:kaby lake soc block diagram.svg|900px]]
  
−
==== Gen9.5 ====
+
==== Gen9.5 LP ====
 
This block is for the most common setup, which is GT2 with 24 execution units.
 
This block is for the most common setup, which is GT2 with 24 execution units.
  
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=== Display ===
 
=== Display ===
−
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/270 rotations.
+
The display has a memory interface (supporting high memory bandwidth coming directly to the display sub-system), a front-end that is responsible for sorting and sequencing the requests (as well as handling things such as rotated displays), and display pipes. The display pipes perform input format conversion, multi-plane composition, color conversion, and scaling the result. The final part of the display port are the prot encoders that convert the input form the display pipes to the appropriate standard used (DP/HDMI/eDP). A number of improvements in Gen9 in the display block were done with respect to the display pipes, specifically being able to consume lossless compression directly without doing any extra unnecessary conversion operations. Additionally the pipes now support render compressed surfaces, Y-tiled surfaces, and on the fly 90/207 rotations.
 
   
 
   
 
[[File:gen9 display block.svg|650px]]
 
[[File:gen9 display block.svg|650px]]
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|-
 
|-
 
|}
 
|}
−
 
−
== Datasheets ==
 
−
=== Programmer's Reference Manual ===
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol01-preface.pdf|Volume 1: Preface]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol02a-commandreference-instructions.pdf|Volume 2a: Command Reference: Instructions (Command Opcodes)]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol02b-commandreference-enumerations.pdf|Volume 2b: Command Reference: Enumerations]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part1.pdf|Volume 2c: Command Reference: Registers Part 1 – Registers A through L]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol02c-commandreference-registers-part2.pdf|Volume 2c: Command Reference: Registers Part 2 – Registers M through Z]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol02d-commandreference-structures.pdf|Volume 2d: Command Reference: Structures]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol03-gpu overview.pdf|Volume 3: GPU Overview]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol04-configurations.pdf|Volume 4: Configurations]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol05-memory views.pdf|Volume 5: Memory Views]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol06-command stream programming.pdf|Volume 6: Command Stream Programming]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol07-3d media gpgpu.pdf|Volume 7: 3D-Media-GPGPU]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol08-media vdbox.pdf|Volume 8: Media VDBOX]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol09-media vebox.pdf|Volume 9: Media Video Enhancement (VEBOX) Engine]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol10-hevc.pdf|Volume 10: HEVC Codec Pipeline (HCP)]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol11-blitter.pdf|Volume 11: Blitter]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol12-display.pdf|Volume 12: Display]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol13-mmio.pdf|Volume 13: Memory-mapped Input/Output (MMIO)]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol14-observability.pdf|Volume 14: Observability]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol15-sfc.pdf|Volume 15: Scaler Format Converter (SFC)]]
 
−
* [[:File:intel-gfx-prm-osrc-kbl-vol16-workarounds.pdf|Volume 16: Workarounds]]
 

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Facts about "Gen9.5 - Microarchitectures - Intel"
RDF feed
codenameGen9.5 +
designerIntel +
first launchedAugust 30, 2016 +
full page nameintel/microarchitectures/gen9.5 +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeGPU +
nameGen9.5 +
process14 nm (0.014 μm, 1.4e-5 mm) +