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(Included the cancellation of Cooper Lake Whitely chips, removed Cascade Lake info, some background on Cooper Lake)
(Correcting Successor and contemporary architectures, fixed cache amounts, added core counts, and removed random designer labeled)
 
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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=2019
+
|introduction=June 18, 2020
−
|process=14 nm
+
|process=14 nm++
 +
|cores=28
 +
|cores 2=24
 +
|cores 3=20
 +
|cores 4=18
 +
|cores 5=16
 +
|cores 6=8
 
|type=Superscalar
 
|type=Superscalar
 
|oooe=Yes
 
|oooe=Yes
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|l1d per=core
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 +
|l1=64 KiB
 +
|l1 per=core
 
|l2=1 MiB
 
|l2=1 MiB
−
|l2 per=core
+
|l2 per=Core
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l3=1.375 MiB
 
|l3=1.375 MiB
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|predecessor=Cascade Lake
 
|predecessor=Cascade Lake
 
|predecessor link=intel/microarchitectures/cascade lake
 
|predecessor link=intel/microarchitectures/cascade lake
−
|successor=Ice Lake (Server)
+
|successor=Sapphire Rapids
−
|successor link=intel/microarchitectures/ice lake (server)
+
|successor link=intel/microarchitectures/sapphire rapids
−
|contemporary=Coffee Lake
+
|contemporary=Ice Lake (Server)
−
|contemporary link=intel/microarchitectures/coffee lake
+
|contemporary link=intel/microarchitectures/ice lake (server)
 +
|contemporary 2=Coffee Lake
 +
|contemporary 2 link=intel/microarchitectures/coffee lake
 
}}
 
}}
−
'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Though announced to be releasing in 1H2020 for all segments, Intel said that, in an effort to streamline their product portfolio, the mainstream version (based on the {{intel|Whitley|l=platform}}) is going to be scrapped and just the {{intel|Cedar Island|l=platform}} chips are going to be released. These are chips that range from 28 to 56 cores, primarily targeted at niche AI and HPC workloads, hence the bfloat16 ([[brain floating-point format]]) support.
+
'''Cooper Lake''' ('''CPL''' / '''CPX''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for the multiprocessing server market only.
  
−
For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
+
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments.
  
 +
For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}.
  
 
== Codenames ==
 
== Codenames ==
 +
Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
 
! Core !! Abbrev !! Target
 
! Core !! Abbrev !! Target
−
|-
+
|- style="text-decoration:line-through"
 
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
 
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
−
|-
+
|- style="text-decoration:line-through"
 
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
 
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
 
|-
 
|-
 
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
 
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
−
|-
+
|- style="text-decoration:line-through"
 
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
 
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
 
|}
 
|}
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== Release Dates ==
 
== Release Dates ==
 
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
 
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
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Cooper Lake is expected to be released in the first half of 2020.
+
Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
  
 
== Process Technology ==
 
== Process Technology ==
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== Architecture ==
 
== Architecture ==
−
Cooper Lake is based on the {{intel|Whitley|l=platform}} platform.
 
 
=== Key changes from {{\\|Cascade Lake}} ===
 
=== Key changes from {{\\|Cascade Lake}} ===
 +
* SoC
 +
** 2x UPI links (6, up from 3)
  
−
{{future information}}
 
−
 
−
* SoC
 
−
** Mainstream 56 cores (up from 28) (note that {{intel|Cascade Lake AP|l=core}} already offered up to 56 cores)
 
−
*** Socketed (from soldered and only sold as part of the S9200WK module)
 
−
** 3-die multi-chip package (up from a single monolithic die)
 
 
* Memory
 
* Memory
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** Higher bandwidth (174.84 GiB/s, up from 119.209 GiB/s)
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** Higher data rate (3200 MT/s, up from 2933 MT/s)
−
** Octa-channel (up from hexa-channel)  
 
 
** Optane DC DIMMs
 
** Optane DC DIMMs
 
*** Apache Pass '''→''' Barlow Pass
 
*** Apache Pass '''→''' Barlow Pass
 +
 
* Platform
 
* Platform
−
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} (mainstream)
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** {{intel|Purley|l=platform}} '''→''' {{intel|Cedar Island|l=platform}}
−
** {{intel|Walker Pass|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} (AP)
+
 
 
* Packaging
 
* Packaging
−
** 4189-contact flip-chip LGA (up from 3647 contacts)
+
** Socket-P+
 +
*** 4189-contact flip-chip LGA (up from 3647 contacts)
 
{{expand list}}
 
{{expand list}}
  

Latest revision as of 18:40, 26 March 2024

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionJune 18, 2020
Process14 nm++
Core Configs28, 24, 20, 18, 16, 8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L1 Cache64 KiB/core
L2 Cache1 MiB/Core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Ice Lake (Server)
Coffee Lake

Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.

Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.

For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.

Codenames[edit]

Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

Cooper Lake and Ice Lake roadmap.

Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.

Process Technology[edit]

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture[edit]

Key changes from Cascade Lake[edit]

  • SoC
    • 2x UPI links (6, up from 3)
  • Memory
    • Higher data rate (3200 MT/s, up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Packaging
    • Socket-P+
      • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions[edit]

Cooper Lake introduced a number of new instructions:

See also[edit]

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Facts about "Cooper Lake - Microarchitectures - Intel"
RDF feed
codenameCooper Lake +
core count28 +, 24 +, 20 +, 18 +, 16 + and 8 +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +