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{{intel title|Cooper Lake|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Cooper Lake
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|designer=Intel
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|manufacturer=Intel
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|introduction=June 18, 2020
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|process=14 nm++
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|cores=28
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|cores 2=24
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|cores 3=20
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|cores 4=18
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|cores 5=16
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|cores 6=8
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|type=Superscalar
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|oooe=Yes
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|speculative=Yes
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|renaming=Yes
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|stages min=14
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|stages max=19
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|isa=x86-64
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|extension=MOVBE
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|extension 2=MMX
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|extension 3=SSE
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|extension 4=SSE2
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|extension 5=SSE3
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|extension 6=SSSE3
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|extension 7=SSE4.1
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|extension 8=SSE4.2
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|extension 9=POPCNT
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|extension 10=AVX
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|extension 11=AVX2
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|extension 12=AES
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|extension 13=PCLMUL
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|extension 14=FSGSBASE
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|extension 15=RDRND
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|extension 16=FMA3
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|extension 17=F16C
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|extension 18=BMI
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|extension 19=BMI2
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|extension 20=VT-x
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|extension 21=VT-d
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|extension 22=TXT
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|extension 23=TSX
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|extension 24=RDSEED
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|extension 25=ADCX
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|extension 26=PREFETCHW
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|extension 27=CLFLUSHOPT
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|extension 28=XSAVE
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|extension 29=SGX
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|extension 30=MPX
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|extension 31=AVX-512
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|l1i=32 KiB
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|l1i per=core
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|l1i desc=8-way set associative
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|l1d=32 KiB
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|l1d per=core
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|l1d desc=8-way set associative
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|l1=64 KiB
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|l1 per=core
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|l2=1 MiB
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|l2 per=Core
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|l2 desc=16-way set associative
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|l3=1.375 MiB
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|l3 per=core
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|l3 desc=11-way set associative
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|core name=Cooper Lake X
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|core name 2=Cooper Lake SP
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|core name 3=Cooper Lake AP
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|predecessor=Cascade Lake
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|predecessor link=intel/microarchitectures/cascade lake
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|successor=Sapphire Rapids
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|successor link=intel/microarchitectures/sapphire rapids
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|contemporary=Ice Lake (Server)
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|contemporary link=intel/microarchitectures/ice lake (server)
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|contemporary 2=Coffee Lake
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|contemporary 2 link=intel/microarchitectures/coffee lake
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}}
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'''Cooper Lake''' ('''CPL''' / '''CPX''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for the multiprocessing server market only.
  
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Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments.
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For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}.
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== Codenames ==
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Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
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{| class="wikitable"
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|-
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! Core !! Abbrev !! Target
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|- style="text-decoration:line-through"
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| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
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|- style="text-decoration:line-through"
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| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
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|-
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| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
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|- style="text-decoration:line-through"
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| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
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|}
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== Brands ==
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{{empty section}}
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== Release Dates ==
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[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
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Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
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== Process Technology ==
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Cooper Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]].
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== Architecture ==
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=== Key changes from {{\\|Cascade Lake}} ===
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* SoC
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** 2x UPI links (6, up from 3)
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* Memory
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** Higher data rate (3200 MT/s, up from 2933 MT/s)
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** Optane DC DIMMs
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*** Apache Pass '''→''' Barlow Pass
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* Platform
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** {{intel|Purley|l=platform}} '''→''' {{intel|Cedar Island|l=platform}}
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* Packaging
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** Socket-P+
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*** 4189-contact flip-chip LGA (up from 3647 contacts)
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{{expand list}}
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====New instructions ====
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Cooper Lake introduced a number of {{x86|extensions|new instructions}}:
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* [[BFLOAT16]] - A new data type for [[acceleration]] of [[neural processor|AI workloads]].
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* {{x86|AVX512 BF16}} - AVX-512 [[Brain Float 16]] extension
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== See also ==
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* {{\\|Ice Lake (Server)}}

Latest revision as of 18:40, 26 March 2024

Edit Values
Cooper Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionJune 18, 2020
Process14 nm++
Core Configs28, 24, 20, 18, 16, 8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L1 Cache64 KiB/core
L2 Cache1 MiB/Core
16-way set associative
L3 Cache1.375 MiB/core
11-way set associative
Cores
Core NamesCooper Lake X,
Cooper Lake SP,
Cooper Lake AP
Succession
Contemporary
Ice Lake (Server)
Coffee Lake

Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.

Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.

For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.

Codenames[edit]

Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.

Core Abbrev Target
Cooper Lake X CPL-X High-end desktops & enthusiasts market
Cooper Lake W CPL-W Enterprise/Business workstations
Cooper Lake SP CPL-SP Server Scalable Processors
Cooper Lake AP CPL-AP Server Advanced Processors

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

Cooper Lake and Ice Lake roadmap.

Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.

Process Technology[edit]

Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.

Architecture[edit]

Key changes from Cascade Lake[edit]

  • SoC
    • 2x UPI links (6, up from 3)
  • Memory
    • Higher data rate (3200 MT/s, up from 2933 MT/s)
    • Optane DC DIMMs
      • Apache Pass → Barlow Pass
  • Packaging
    • Socket-P+
      • 4189-contact flip-chip LGA (up from 3647 contacts)

This list is incomplete; you can help by expanding it.

New instructions[edit]

Cooper Lake introduced a number of new instructions:

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cooper_lake&oldid=102375"
Facts about "Cooper Lake - Microarchitectures - Intel"
RDF feed
codenameCooper Lake +
core count28 +, 24 +, 20 +, 18 +, 16 + and 8 +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +