Editing intel/microarchitectures/comet lake

{{intel title|Comet Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Comet Lake
|designer=Intel
|manufacturer=Intel
|process=14 nm
|cores=4
|type=Superscalar
|type 2=Superpipeline
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=5-way
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|l1i=32 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=256 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=2 MiB
|l3 per=core
|l3 desc=Up to 16-way set associative
|l4=128 MiB
|l4 per=package
|l4 desc=on Iris Pro GPUs only
|core name=Comet Lake U
|core name 2=Comet Lake S
|predecessor=Coffee Lake
|predecessor link=intel/microarchitectures/coffee lake
|predecessor 2=Whiskey Lake
|predecessor 2 link=intel/microarchitectures/whiskey lake
|successor=Rocket Lake
|successor link=intel/microarchitectures/rocket lake
}}
'''Comet Lake''' ('''CML''') is [[Intel]]'s successor to {{\\|Coffee Lake}}, an enhanced [[14 nm process]] [[microarchitecture]] for mainstream desktops and mobile devices.

For desktop and mobile, Comet Lake is branded as 10th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}}, and {{intel|Core i9}} processors.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Description !! Graphics !! Target
|-
| {{intel|Comet Lake S|l=core}} || CML-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
|-
| {{intel|Comet Lake U|l=core}} || CML-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|}

== Brands ==
Intel is expected to release Comet Lake under 3 main brand families:

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
|-
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance ||  || 
|-
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance ||  || 
|-
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance ||  || 
|-
| || {{intel|Core i9}} || High-end/Enthusiasts Performance ||  || 
|}

== Release Dates ==
Comet Lake processors were introduced in a number of phases. Initial mobile processors were launched on August 21, 2019. Intel followed up with the remaining desktop parts on April 30, 2020. Enterprise and vPro models were followed on May 13, 2020.

== Compatibility ==
There are no official drivers by Intel for [[Windows 7]] or [[Windows 8]]. [[Microsoft]] announced that only [[Windows 10]] will have support for Kaby Lake. [[Linux]] added initial support for Kaby Lake starting with Linux Kernel 4.5.

{| class="wikitable"
! Vendor !! OS  !! Version !! Notes
|-
| rowspan="3" | [[Microsoft]] || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
|-
| style="background-color: #ffdad6;" | Windows 8 || No Support
|-
| style="background-color: #d6ffd8;" | Windows 10 || Support
|- 
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.5 || Initial Support (Fedora 24, Yocto v2.2, ..)
|-
| Google || Chromium || style="background-color: #d6ffd8;" | Chromium || Support
|-
| Wind River || VxWorks || style="background-color: #d6ffd8;" | VxWorks 7 || Support
|}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
|}

=== CPUID ===
{{further|intel/cpuid|l1=Intel CPUIDs}}
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
|-
| rowspan="2" | {{intel|Comet Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xC
|-
| colspan="5" | Family 6 Model 142 Stepping 12
|-
| rowspan="2" | {{intel|Comet Lake S|S|l=core}}/{{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || 0x0-0x5
|-
| colspan="5" | Family 6 Model 165 Stepping 0-5<br>Stepping: G0=0, P0=1, R1=2, G1=3, P1=4, Q0=5
|}

== Architecture ==
=== Key changes from {{\\|Coffee Lake}}===
* Enhanced "14nm++" process results in higher turbo frequencies

* System Architecture
** 25% more [[cores]] (up to 10, from 8)
** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB)

* Chipset
** {{intel|Cannon Point|300 Series chipset|l=chipset}} → {{intel|Canon Point|400 Series chipset|l=chipset}}
*** 2.5G Ethernet (Foxville) support
*** IntegratedWiFi 6 AX201 (GiG+) support via {{intel|CNVi}}

* Memory
** Faster memory for mainstream desktops (i.e., {{intel|Comet  Lake S|l=core}}) DDR4-2933 (from DDR4-2666)

* Graphics
** {{intel|Gen 9.5|l=arch}} GPUs (No Change)

* Packaging
** [[Die thinning]] on top-end SKUs for better heat removal

{{expand list}}

=== Block Diagram ===
{{empty section}}

==== Gen9.5 ====
See {{intel|Gen9.5#Gen9.5|l=arch}}.

=== Memory Hierarchy ===
The overall memory structure is identical to {{\\|Skylake}}.

<!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
* Cache
** L0 µOP cache:
*** 1,536 µOPs, 8-way set associative
**** 32 sets, 6-µOP line size
**** statically divided between threads, per core, inclusive with L1I
** L1I Cache:
*** 32 [[KiB]], 8-way set associative
**** 64 sets, 64 B line size
**** shared by the two threads, per core
** L1D Cache:
*** 32 KiB, 8-way set associative
*** 64 sets, 64 B line size
*** shared by the two threads, per core
*** 4 cycles for fastest load-to-use (simple pointer accesses)
**** 5 cycles for complex addresses
*** 64 B/cycle load bandwidth
*** 32 B/cycle store bandwidth
*** Write-back policy
** L2 Cache:
*** Unified, 256 KiB, 4-way set associative
*** Non-inclusive
*** 1024 sets, 64 B line size
*** 12 cycles for fastest load-to-use
*** 64 B/cycle bandwidth to L1$
*** Write-back policy
** L3 Cache/LLC:
*** Up to 2 MiB Per core, shared across all cores
*** Up to 16-way set associative
*** Inclusive
*** 64 B line size
*** Write-back policy
*** Per each core:
**** Read: 32 B/cycle (@ ring [[clock]])
**** Write: 32 B/cycle (@ ring clock)
*** 42 cycles for fastest load-to-use
** Side Cache:
*** 64 MiB & 128 MiB [[eDRAM]]
*** Per package
*** Only on the Iris Pro GPUs
*** Read: 32 B/cycle (@ [[eDRAM]] clock)
*** Write: 32 B/cycle (@ eDRAM clock)
** System [[DRAM]]:
*** 2 Channels
*** 8 B/cycle/channel (@ memory clock)
*** 42 cycles + 51 ns latency

Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
* TLBs:
** ITLB
*** 4 KiB page translations:
**** 128 entries; 8-way set associative
**** dynamic partitioning
*** 2 MiB / 4 MiB page translations:
**** 8 entries per thread; fully associative
**** Duplicated for each thread
** DTLB
*** 4 KiB page translations:
**** 64 entries; 4-way set associative
**** fixed partition
*** 2 MiB / 4 MiB page translations:
**** 32 entries; 4-way set associative
**** fixed partition
*** 1G page translations:
**** 4 entries; 4-way set associative
**** fixed partition
** STLB
*** 4 KiB + 2 MiB page translations:
**** 1536 entries; 12-way set associative
**** fixed partition
*** 1 GiB page translations:
**** 16 entries; 4-way set associative
**** fixed partition
<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->


* '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.

== Overview ==
{{empty section}}

== Configurability ==
{{empty section}}

== Graphics ==
{{empty section}}

== Die ==
{{empty section}}

== All Comet Lake Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc7 tc8 tc20 tc21">
{{comp table header|main|20:List of Comet Lake-based Processors}}
{{comp table header|main|9:Main processor|2:Frequencies|Memory|3:GPU|2:Features}}
{{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|Max Turbo|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Comet Lake]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?platform
 |?core name
 |?core count
 |?thread count
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |format=template
 |template=proc table 3
 |userparam=19:20
 |mainlabel=-
 |limit=200
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::CometLake]]}}
</table>
{{comp table end}}

== See also ==
* AMD {{amd|Zen 2|l=arch}}
codename	Comet Lake +
core count	4 +
designer	Intel +
full page name	intel/microarchitectures/comet lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Comet Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +