Latest revision |
Your text |
Line 85: |
Line 85: |
| | | |
| == Brands == | | == Brands == |
− | Intel has released Comet Lake under 4 main brand families: | + | Intel is expected to release Comet Lake under 3 main brand families: |
| | | |
| {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" |
Line 93: |
Line 93: |
| ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] |
| |- | | |- |
− | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || || |
| |- | | |- |
− | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || || |
| |- | | |- |
− | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || || |
| |- | | |- |
− | | [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || Ultra Performance || [[deca-core|Deca]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | || {{intel|Core i9}} || High-end/Enthusiasts Performance || || |
| |} | | |} |
| | | |
Line 176: |
Line 176: |
| ** [[Die thinning]] on top-end SKUs for better heat removal | | ** [[Die thinning]] on top-end SKUs for better heat removal |
| | | |
− | {{expand list}} | + | {{expand section}} |
| | | |
− | === Block Diagram === | + | == See also == |
− | {{empty section}}
| + | * AMD {{amd|Zen 2|l=arch}} |
− | | |
− | ==== Gen9.5 ====
| |
− | See {{intel|Gen9.5#Gen9.5|l=arch}}. | |
− | | |
− | === Memory Hierarchy ===
| |
− | The overall memory structure is identical to {{\\|Skylake}}.
| |
− | | |
− | <!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
| |
− | * Cache
| |
− | ** L0 µOP cache:
| |
− | *** 1,536 µOPs, 8-way set associative
| |
− | **** 32 sets, 6-µOP line size
| |
− | **** statically divided between threads, per core, inclusive with L1I
| |
− | ** L1I Cache:
| |
− | *** 32 [[KiB]], 8-way set associative
| |
− | **** 64 sets, 64 B line size
| |
− | **** shared by the two threads, per core
| |
− | ** L1D Cache:
| |
− | *** 32 KiB, 8-way set associative
| |
− | *** 64 sets, 64 B line size
| |
− | *** shared by the two threads, per core
| |
− | *** 4 cycles for fastest load-to-use (simple pointer accesses)
| |
− | **** 5 cycles for complex addresses
| |
− | *** 64 B/cycle load bandwidth
| |
− | *** 32 B/cycle store bandwidth
| |
− | *** Write-back policy
| |
− | ** L2 Cache:
| |
− | *** Unified, 256 KiB, 4-way set associative
| |
− | *** Non-inclusive
| |
− | *** 1024 sets, 64 B line size
| |
− | *** 12 cycles for fastest load-to-use
| |
− | *** 64 B/cycle bandwidth to L1$
| |
− | *** Write-back policy
| |
− | ** L3 Cache/LLC:
| |
− | *** Up to 2 MiB Per core, shared across all cores
| |
− | *** Up to 16-way set associative
| |
− | *** Inclusive
| |
− | *** 64 B line size
| |
− | *** Write-back policy
| |
− | *** Per each core:
| |
− | **** Read: 32 B/cycle (@ ring [[clock]])
| |
− | **** Write: 32 B/cycle (@ ring clock)
| |
− | *** 42 cycles for fastest load-to-use
| |
− | ** Side Cache:
| |
− | *** 64 MiB & 128 MiB [[eDRAM]]
| |
− | *** Per package
| |
− | *** Only on the Iris Pro GPUs
| |
− | *** Read: 32 B/cycle (@ [[eDRAM]] clock)
| |
− | *** Write: 32 B/cycle (@ eDRAM clock)
| |
− | ** System [[DRAM]]:
| |
− | *** 2 Channels
| |
− | *** 8 B/cycle/channel (@ memory clock)
| |
− | *** 42 cycles + 51 ns latency
| |
− | | |
− | Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
| |
− | * TLBs:
| |
− | ** ITLB
| |
− | *** 4 KiB page translations:
| |
− | **** 128 entries; 8-way set associative
| |
− | **** dynamic partitioning
| |
− | *** 2 MiB / 4 MiB page translations:
| |
− | **** 8 entries per thread; fully associative
| |
− | **** Duplicated for each thread
| |
− | ** DTLB
| |
− | *** 4 KiB page translations:
| |
− | **** 64 entries; 4-way set associative
| |
− | **** fixed partition
| |
− | *** 2 MiB / 4 MiB page translations:
| |
− | **** 32 entries; 4-way set associative
| |
− | **** fixed partition
| |
− | *** 1G page translations:
| |
− | **** 4 entries; 4-way set associative
| |
− | **** fixed partition
| |
− | ** STLB
| |
− | *** 4 KiB + 2 MiB page translations:
| |
− | **** 1536 entries; 12-way set associative
| |
− | **** fixed partition
| |
− | *** 1 GiB page translations:
| |
− | **** 16 entries; 4-way set associative
| |
− | **** fixed partition
| |
− | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
| |
− | | |
− | | |
− | * '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value. | |
− | | |
− | == Overview ==
| |
− | {{empty section}}
| |
− | | |
− | == Configurability ==
| |
− | {{empty section}}
| |
− | | |
− | == Graphics ==
| |
− | {{empty section}}
| |
− | | |
− | == Die ==
| |
− | {{empty section}} | |
− | | |
− | == All Comet Lake Chips ==
| |
− | <!-- NOTE:
| |
− | This table is generated automatically from the data in the actual articles.
| |
− | If a microprocessor is missing from the list, an appropriate article for it needs to be
| |
− | created and tagged accordingly.
| |
− | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| |
− | -->
| |
− | {{comp table start}}
| |
− | <table class="comptable sortable tc7 tc8 tc20 tc21">
| |
− | {{comp table header|main|20:List of Comet Lake-based Processors}}
| |
− | {{comp table header|main|9:Main processor|2:Frequencies|Memory|3:GPU|2:Features}}
| |
− | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|Max Turbo|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Comet Lake]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?microprocessor family
| |
− | |?platform
| |
− | |?core name
| |
− | |?core count
| |
− | |?thread count
| |
− | |?l3$ size
| |
− | |?tdp
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?max memory#GiB
| |
− | |?integrated gpu
| |
− | |?integrated gpu base frequency
| |
− | |?integrated gpu max frequency
| |
− | |?has intel turbo boost technology 2_0
| |
− | |?has simultaneous multithreading
| |
− | |format=template
| |
− | |template=proc table 3
| |
− | |userparam=19:20
| |
− | |mainlabel=-
| |
− | |limit=200
| |
− | }}
| |
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::CometLake]]}}
| |
− | </table>
| |
− | {{comp table end}}
| |