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| | == Brands == | | == Brands == |
| − | Intel has released Comet Lake under 4 main brand families: | + | Intel is expected to release Comet Lake under 3 main brand families: |
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| | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" |
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| | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] |
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| − | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || || |
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| − | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || || |
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| − | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || || |
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| − | | [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || Ultra Performance || [[deca-core|Deca]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | + | | || {{intel|Core i9}} || High-end/Enthusiasts Performance || || |
| | |} | | |} |
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| | === CPUID === | | === CPUID === |
| − | {{further|intel/cpuid|l1=Intel CPUIDs}} | + | {{empty section}} |
| − | {| class="wikitable tc1 tc2 tc3 tc4 tc5"
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| − | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
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| − | |-
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| − | | rowspan="2" | {{intel|Comet Lake U|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xC
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| − | |-
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| − | | colspan="5" | Family 6 Model 142 Stepping 12
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| − | |-
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| − | | rowspan="2" | {{intel|Comet Lake S|S|l=core}}/{{intel|Comet Lake H|H|l=core}} || 0 || 0x6 || 0xA || 0x5 || 0x0-0x5
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| − | |-
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| − | | colspan="5" | Family 6 Model 165 Stepping 0-5<br>Stepping: G0=0, P0=1, R1=2, G1=3, P1=4, Q0=5
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| − | |}
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| | == Architecture == | | == Architecture == |
| | === Key changes from {{\\|Coffee Lake}}=== | | === Key changes from {{\\|Coffee Lake}}=== |
| − | * Enhanced "14nm++" process results in higher turbo frequencies
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| − |
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| − | * System Architecture
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| − | ** 25% more [[cores]] (up to 10, from 8)
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| − | ** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB)
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| − |
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| − | * Chipset
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| − | ** {{intel|Cannon Point|300 Series chipset|l=chipset}} → {{intel|Canon Point|400 Series chipset|l=chipset}}
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| − | *** 2.5G Ethernet (Foxville) support
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| − | *** IntegratedWiFi 6 AX201 (GiG+) support via {{intel|CNVi}}
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| − |
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| − | * Memory
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| − | ** Faster memory for mainstream desktops (i.e., {{intel|Comet Lake S|l=core}}) DDR4-2933 (from DDR4-2666)
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| − |
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| − | * Graphics
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| − | ** {{intel|Gen 9.5|l=arch}} GPUs (No Change)
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| − |
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| − | * Packaging
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| − | ** [[Die thinning]] on top-end SKUs for better heat removal
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| − |
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| − | {{expand list}}
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| − |
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| − | === Block Diagram ===
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| − | {{empty section}}
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| − |
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| − | ==== Gen9.5 ====
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| − | See {{intel|Gen9.5#Gen9.5|l=arch}}.
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| − |
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| − | === Memory Hierarchy ===
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| − | The overall memory structure is identical to {{\\|Skylake}}.
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| − |
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| − | <!-- ===================== START IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
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| − | * Cache
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| − | ** L0 µOP cache:
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| − | *** 1,536 µOPs, 8-way set associative
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| − | **** 32 sets, 6-µOP line size
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| − | **** statically divided between threads, per core, inclusive with L1I
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| − | ** L1I Cache:
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| − | *** 32 [[KiB]], 8-way set associative
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| − | **** 64 sets, 64 B line size
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| − | **** shared by the two threads, per core
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| − | ** L1D Cache:
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| − | *** 32 KiB, 8-way set associative
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| − | *** 64 sets, 64 B line size
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| − | *** shared by the two threads, per core
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| − | *** 4 cycles for fastest load-to-use (simple pointer accesses)
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| − | **** 5 cycles for complex addresses
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| − | *** 64 B/cycle load bandwidth
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| − | *** 32 B/cycle store bandwidth
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| − | *** Write-back policy
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| − | ** L2 Cache:
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| − | *** Unified, 256 KiB, 4-way set associative
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| − | *** Non-inclusive
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| − | *** 1024 sets, 64 B line size
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| − | *** 12 cycles for fastest load-to-use
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| − | *** 64 B/cycle bandwidth to L1$
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| − | *** Write-back policy
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| − | ** L3 Cache/LLC:
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| − | *** Up to 2 MiB Per core, shared across all cores
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| − | *** Up to 16-way set associative
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| − | *** Inclusive
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| − | *** 64 B line size
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| − | *** Write-back policy
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| − | *** Per each core:
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| − | **** Read: 32 B/cycle (@ ring [[clock]])
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| − | **** Write: 32 B/cycle (@ ring clock)
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| − | *** 42 cycles for fastest load-to-use
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| − | ** Side Cache:
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| − | *** 64 MiB & 128 MiB [[eDRAM]]
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| − | *** Per package
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| − | *** Only on the Iris Pro GPUs
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| − | *** Read: 32 B/cycle (@ [[eDRAM]] clock)
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| − | *** Write: 32 B/cycle (@ eDRAM clock)
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| − | ** System [[DRAM]]:
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| − | *** 2 Channels
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| − | *** 8 B/cycle/channel (@ memory clock)
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| − | *** 42 cycles + 51 ns latency
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| − |
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| − | Coffee Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
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| − | * TLBs:
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| − | ** ITLB
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| − | *** 4 KiB page translations:
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| − | **** 128 entries; 8-way set associative
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| − | **** dynamic partitioning
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| − | *** 2 MiB / 4 MiB page translations:
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| − | **** 8 entries per thread; fully associative
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| − | **** Duplicated for each thread
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| − | ** DTLB
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| − | *** 4 KiB page translations:
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| − | **** 64 entries; 4-way set associative
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| − | **** fixed partition
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| − | *** 2 MiB / 4 MiB page translations:
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| − | **** 32 entries; 4-way set associative
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| − | **** fixed partition
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| − | *** 1G page translations:
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| − | **** 4 entries; 4-way set associative
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| − | **** fixed partition
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| − | ** STLB
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| − | *** 4 KiB + 2 MiB page translations:
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| − | **** 1536 entries; 12-way set associative
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| − | **** fixed partition
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| − | *** 1 GiB page translations:
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| − | **** 16 entries; 4-way set associative
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| − | **** fixed partition
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| − | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON SKYLAKE !! ============================= -->
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| − |
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| − |
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| − | * '''Note:''' STLB is incorrectly reported as "6-way" by CPUID leaf 2 (EAX=02H). Coffee Lake erratum CFL084 recommends software to simply ignore that value.
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| − |
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| − | == Overview ==
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| − | {{empty section}}
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| − |
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| − | == Configurability ==
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| − | {{empty section}}
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| − |
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| − | == Graphics ==
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| | {{empty section}} | | {{empty section}} |
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| − | == Die == | + | == See also == |
| − | {{empty section}} | + | * AMD {{amd|Zen 2|l=arch}} |
| − | | |
| − | == All Comet Lake Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − | | |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc7 tc8 tc20 tc21">
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| − | {{comp table header|main|20:List of Comet Lake-based Processors}}
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| − | {{comp table header|main|9:Main processor|2:Frequencies|Memory|3:GPU|2:Features}}
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| − | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|Max Turbo|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}
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| − | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Comet Lake]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?platform
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l3$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?integrated gpu max frequency
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=19:20
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| − | |mainlabel=-
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| − | |limit=200
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::CometLake]]}}
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| − | </table>
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| − | {{comp table end}}
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