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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|manufacturer 2=dell
 
 
|introduction=October 5, 2017
 
|introduction=October 5, 2017
 
|process=14 nm
 
|process=14 nm
 +
|cores=2
 +
|cores 2=4
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|cores 3=6
 
|type=Superscalar
 
|type=Superscalar
 
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|type 2=Superpipeline
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|extension 7=SSE4.1
 
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|extension 8=SSE4.2
 
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|extension 9=POPCNT
 
|extension 10=AVX
 
|extension 10=AVX
 
|extension 11=AVX2
 
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|extension 12=AES
 
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|extension 13=PCLMUL
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|extension 16=FMA3
 
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|extension 28=XSAVE
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|l1i=32 KiB
 
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|l1i per=core
 
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|core name 2=Coffee Lake H
 
|core name 2=Coffee Lake H
 
|core name 3=Coffee Lake S
 
|core name 3=Coffee Lake S
|core name 4=Coffee Lake R
 
|core name 5=Coffee Lake E
 
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
|successor=Comet Lake
+
|successor=Ice Lake
|successor link=intel/microarchitectures/comet lake
+
|successor link=intel/microarchitectures/ice lake (client)
|successor 2=Ice Lake
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|successor 2=Whiskey Lake
|successor 2 link=intel/microarchitectures/ice lake (client)
+
|successor 2 link=intel/microarchitectures/whiskey_lake
|contemporary=Whiskey Lake
 
|contemporary link=intel/microarchitectures/whiskey_lake
 
|contemporary 2=Cannon Lake
 
|contemporary 2 link=intel/microarchitectures/cannon_lake
 
 
}}
 
}}
'''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel. In [[2018]], Intel refreshed the Coffee Lake lineup to incorporate their first series of mainstream [[octa-core]] processors.
+
'''Coffee Lake''' ('''CFL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for desktops and high-performance mobile devices. Coffee Lake was introduced in the third quarter of [[2017]] and is manufactured on Intel's mature [[14 nm process]]. Coffee Lake features the first series of mainstream [[hexa-core]] processors from Intel.
  
 
== Codenames ==
 
== Codenames ==
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! Core !! Abbrev !! Platform !! Description !! Graphics !! Target
+
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
|-
| {{intel|Coffee Lake U|l=core}} || CFL-U || || Ultra-low power|| GT3e || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
+
| {{intel|Coffee Lake U|l=core}} || CFL-U || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|-
 
|-
| {{intel|Coffee Lake H|l=core}} || CFL-H || || High-performance graphics || GT2 || Ultimate mobile performance, mobile workstations
+
| {{intel|Coffee Lake H|l=core}} || CFL-H || High-performance graphics || GT3e || Ultimate mobile performance, mobile workstations
 
|-
 
|-
| {{intel|Coffee Lake S|l=core}} || CFL-S || || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
+
| {{intel|Coffee Lake S|l=core}} || CFL-S || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
 
|-
 
|-
| {{intel|Coffee Lake R|l=core}} || CFL-R || || Mainstream performance (Refresh) || GT2 || Desktop performance to value, AiOs, and minis
+
| {{intel|Coffee Lake X|l=core}} || CFL-X || Extreme Performance || || High performance desktops
|-
 
| {{intel|Coffee Lake E|l=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers
 
 
|}
 
|}
  
 
== Brands ==
 
== Brands ==
Intel released Coffee Lake under 6 main brand families:
+
Intel released Coffee Lake under 3 main brand families:
  
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
 
|-
 
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | Generation !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
+
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
 
|-
 
|-
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
 
|-
 
|-
| [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
 
|-
 
|-
| [[File:intel pentium (2015).png|50px|link=intel/pentium]] || {{intel|Pentium Gold}} || 5xxx || Budget || [[dual-core|Dual]] || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
|-
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || 8th/9th Gen || Low-end Performance || [[quad-core|Quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
+
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
 
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || 8th/9th Gen || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || 8th/9th Gen || High-end Performance || Hexa || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
|-
 
| [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || 9th Gen || Ultra Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
 
|}
 
|}
  
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Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.
 
Intel announced Coffee Lake-based SKUs on September 24 with products available beginning October 5, 2017 and OEM systems starting Q4 2017.
 
In October 2018, Intel introduced a refresh of Coffee Lake, adding more cores and increasing their clock frequencies.
 
  
 
{{clear}}
 
{{clear}}
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[[File:intel 14nm++.png|400px|right]]
 
[[File:intel 14nm++.png|400px|right]]
 
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
 
{{see also|intel/microarchitectures/broadwell#Process_Technology|14 nm lithography process|l1=Broadwell § Process Technology}}
Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides up to 26% more performance at the same power or 52% less power at the same performance.
+
Coffee Lake is manufactured on [[Intel]]'s 3rd generation [[14 nm process]] called "14nm++". The process is the second enhanced version of the first which was used for the {{\\|Broadwell}} microarchitecture (first enhanced version was first used for {{\\|Kaby Lake}}). The various enhancements improve performance without increasing the capacitance (i.e., active power characteristics). 14nm++ allows for +23-24% higher drive current. Intel claims their 14nm++ process provides 26% more performance for 52% less power.
  
  
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=== CPUID ===
 
=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
+
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
+
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
 
| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 6 || 0x6 || 0x8 || 0xE || 0xA
 
 
|-
 
|-
| colspan="5" | Family 6 Model 142 Stepping 10
+
| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE
 
|-
 
|-
| rowspan="2" | {{intel|Coffee Lake S|S|l=core}}/{{intel|Coffee Lake H|H|l=core}} || 0 || 0x6 || 0x9 || 0xE || 0xA
+
| colspan="4" | Family 6 Model 158
 
|-
 
|-
| colspan="5" | Family 6 Model 158 Stepping 10
+
| rowspan="2" | {{intel|Coffee Lake U|U|l=core}} || 0 || 0x6 || 0x? || 0x?
 
|-
 
|-
| rowspan="2" | i3-9350KF || 0 || 0x6 || 0x9 || 0xE || 0xB
+
| colspan="4" | Family 6 Model ???
|-
 
| colspan="5" | Family 6 Model 158 Stepping 11
 
|-
 
| rowspan="2" | 94xx-99xx || 0 || 0x6 || 0x9 || 0xE || 0xC,0xD
 
|-
 
| colspan="5" | Family 6 Model 158 Stepping 12,13
 
 
|}
 
|}
 
Meltdown and L1TF are fixed in hardware starting with stepping 12. Stepping 13 adds mitigation against Speculative Store Bypass.
 
  
 
== Architecture ==
 
== Architecture ==
 
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]]
 
[[File:intel 8th gen core logs.png|right|thumb|250px|Coffee Lake is 8th Generation Core]]
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50% (later by 100%), enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]].
+
While there is no change in pure IPC over Skylake and the actual microarchitecture is largely the same, Intel introduced a number of major architectural changes in Coffee Lake. In addition to improved performance brought by the uplift in [[binning]] as a result of the enhanced process, Coffee Lake also increased the number of cores by 50%, enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake chips to be highly [[overclockable]].
  
 
=== Key changes from {{\\|Kaby Lake}}===
 
=== Key changes from {{\\|Kaby Lake}}===
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** 50% more [[physical core|cores]] (6, from 4)
 
** 50% more [[physical core|cores]] (6, from 4)
 
** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
 
** 50% larger [[last level cache]] (up to 12 MiB, from 8 MiB)
** Coffee Lake Refresh
+
 
*** 100% more [[physical core|cores]] (8, from 4)
+
* Core
*** 100% larger [[last level cache]] (up to 16 MiB, from 8 MiB)
+
** LSD has been re-enabled (Previously {{\\|skylake_(server)#Front-end|disabled}})
  
 
* Chipset
 
* Chipset
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
+
** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset (Cannon Lake PCH)
 
*** Integrated USB 3.1 (10 Gib/s)
 
*** Integrated USB 3.1 (10 Gib/s)
 
**** Up to 6 ports
 
**** Up to 6 ports
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** {{intel|Core i5}}
 
** {{intel|Core i5}}
 
*** i5-7000 '''→''' i5-8000
 
*** i5-7000 '''→''' i5-8000
*** 2400 MT/s '''→''' 2666 MT/s
+
*** 2666 MT/s '''→''' 2666 MT/s
 
*** [[quad-core]] '''→''' [[hexa-core]]
 
*** [[quad-core]] '''→''' [[hexa-core]]
 
*** 6 MiB [[L3]] '''→''' 9 MiB [[L3]]
 
*** 6 MiB [[L3]] '''→''' 9 MiB [[L3]]
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==== Entire SoC Overview (hexa) ====
 
==== Entire SoC Overview (hexa) ====
 
[[File:coffee lake soc block diagram.svg|900px]]
 
[[File:coffee lake soc block diagram.svg|900px]]
 
==== Entire SoC Overview (octa) ====
 
[[File:coffee lake r soc block diagram.svg|1000px]]
 
  
 
==== Individual Core ====
 
==== Individual Core ====
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**** fixed partition
 
**** fixed partition
 
*** 1G page translations:
 
*** 1G page translations:
**** 4 entries; 4-way set associative
+
**** 4 entries; fully associative
 
**** fixed partition
 
**** fixed partition
 
** STLB
 
** STLB
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=== Historical Trend ===
 
=== Historical Trend ===
Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecture since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). The Core i7-980X was also the first hexa-core consumer chip, although it was part of the enthusiast market segment and used a larger die.
+
Coffee Lake presents the largest change in the system architecture of Intel's mainstream microarchitecutre since the introduction of {{\\|sandy_bridge_(client)#System_Architecture|Sandy Bridge}} in [[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=core}} core. Those initial quad-cores comprised of two separate dies interconnected in a [[multi-chip package]]. A coherent communication link was lacking and the aging [[front-side bus]] was used for as the die-to-die link. This configuration did not change through {{\\|Penryn}} up until the introduction of the Core i7 based on the {{\\|Nehalem}} microarchitecture in [[2008]]. Nehalem leveraged [[Moore's Law]] and Intel's [[45 nm process]] to incorporate all four cores onto a single die along with a large number of changes, particularly enhancing the uncore (now known as the System Agent). The Core i7-980X was also the first hexa-core consumer chip, although it was part of the enthusiast market segment and used a larger die.
  
  
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With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge.
 
With the introduction of {{\\|Sandy Bridge}} in 2011, the entire system architecture was reworked. A particular goal of Sandy Bridge was {{\\|Sandy Bridge#Configurability|its configurability}}. Intel wanted to be able to use a single design across multiple market segments without having to spend extra resources on multiple physical designs. A large part of its modularity came from the {{\\|sandy_bridge_(client)#Ring_Interconnect|ring interconnect Sandy Bridge implemented}}. It's worth pointing out that the ring implementation in Sandy Bridge is an enhanced version largely based on an implementation first incorporated into the Nehalem-EX server parts. The ring allowed Intel to integrate the {{intel|System Agent}} and the [[integrated graphics]] on-die in Sandy Bridge.
 
[[File:sandy bridge ring scalability.svg|right|100px]]
 
[[File:sandy bridge ring scalability.svg|right|100px]]
Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip (SoC) with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.
+
Each of those components had its own ring agent (in addition to the individual core), allowing for efficient transfer of data between the GPU, the SA, and the individual cores and caches. The final result was a complete system on a chip with four cores and a 12 EU GPU on a single die measuring consisting of 1.16 billion transistors on a 216 mm² die.
  
  
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::[[File:sandy bridge-coffee lake overview change.svg|600px]]
+
::[[File:sandy bridge-coffee lake overview change.svg|500px|left]]
  
  
[[File:quad to hexa mainstream die areas.svg|thumb|right|die size over time]]
+
[[File:quad to hexa mainstream die areas.svg|500px|right]]
 
+
It can easily be seen how the natural evolution of [[Moore's Law]] and its affects on the die size of Intel's mainstream platform enables the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices contributed an extra ~25mm². In fact, it can further be seen that even an 8-core Coffee Lake would be smaller than Haswell's quad-core at around 174 mm².  It's worth noting that Coffee Lake is released concurrently with {{\\|Cannon Lake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well.
 
 
Intel's rather faithful [[process shrink]] which has resulted in over 2.4x cell-level density improvement had a significant impact on the die size of their mainstream platform which enabled the addition of two more cores and their associated cache slices without sacrificing yield due to a bigger die. In fact, the hexa-core at 149 mm² is still considerably smaller than even the quad-core {{\\|Haswell}}-based chips. The pair of cores with their associated cache slices and the {{intel|ring interconnect}} agent contributed an extra ~25mm².
 
 
 
 
 
:[[File:coffee lake ring explanation 1.svg|600px]]
 
 
 
:[[File:coffee lake ring addition.png|600px]]
 
 
 
 
 
In late 2018 Intel introduced a refresh of Coffee Lake which further bumped the core count to eight. The 8-core refresh still yielded a smaller die than Haswell's quad-core, at around 174 mm².  It's worth noting that Coffee Lake is released concurrently with {{\\|Cannon Lake}} which is a [[10 nm]]-based microarchitecture for low-power mobile devices. Due to Intel's faithful [[die shrink]] of roughly x2.7 in density, an identical [[hexa-core]] Coffee Lake die on 10nm would result in a smaller die than any of the [[14 nm]] quad-core dies, possibly even the [[dual-core]] dies as well.
 
 
 
::[[File:coffee lake-coffee lake refresh overview change.svg|600px]]
 
  
 
{{clear}}
 
{{clear}}
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==== Front-end ====
 
==== Front-end ====
 
+
Note that a bug associated with the Loop Stream Detector (LSD) has been fixed with Coffee Lake. See {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}.
The LSD remains disabled in Coffee Lake, see {{\\|skylake_(server)#Front-end|Skylake (server) § Front-end}}.
 
  
 
==== Scheduler Ports & Execution Units ====
 
==== Scheduler Ports & Execution Units ====
Line 405: Line 382:
 
<tr><th>Port 2</th><td>Load, AGU</td></tr>
 
<tr><th>Port 2</th><td>Load, AGU</td></tr>
 
<tr><th>Port 3</th><td>Load, AGU</td></tr>
 
<tr><th>Port 3</th><td>Load, AGU</td></tr>
<tr><th>Port 4</th><td>Store</td></tr>
+
<tr><th>Port 4</th><td>Store, AGU</td></tr>
 
<tr><th>Port 7</th><td>AGU</td></tr>
 
<tr><th>Port 7</th><td>AGU</td></tr>
 
</table>
 
</table>
Line 441: Line 418:
 
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 
|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 
|}
 
|}
 +
 +
=== Overclockability ===
 +
These results are obtained with an AVX offset of -2.
 +
{| class="wikitable"
 +
|-
 +
! Clock Speed !! I7 8700k !! I5 8600k !! Vcore
 +
|-
 +
| 5.3 Ghz|| 3% || 13%|| 1.437V
 +
|-
 +
| 5.2Ghz|| 22% || 38% || 1.425V
 +
|-
 +
| 5.1Ghz|| 54%|| 66%|| 1.412V
 +
|-
 +
| 5.0Ghz|| 88% || 85%|| 1.40V
 +
|-
 +
| 4.9Ghz|| 99%|| 96%  || 1.387V
 +
|}
 +
Source.<ref>[https://siliconlottery.com/collections/coffeelake], Silicon Lottery, Coffee Lake CPUs.</ref>
  
 
== Configurability ==
 
== Configurability ==
Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die followed by the first octa-core die. Currently, the Coffee Lake family consists of four dies, aimed towards the high-performance market.
+
Coffee Lake builds upon the Skylake platform, with the addition of the first hexa core die. Currently, the Coffee Lake family consists out of three dies, that are aimed towards the high performance market.
 
   
 
   
 
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left">
 
<gallery widths=300px heights=150px caption="Physical Layout Breakdown" style="float:left">
Line 465: Line 460:
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux
 
|-
 
|-
| {{intel|UHD Graphics 630}} || 12/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0'''
+
| {{intel|UHD Graphics 630}} || 23/24 || GT2 || {{intel|Coffee Lake S|S|l=core}} || - || colspan="2" style="text-align: center;" | '''1.0''' || style="text-align: center;" | '''12''' || style="text-align: center;" | '''N/A''' || style="text-align: center;" | '''5.1''' || style="text-align: center;" | '''4.5''' || style="text-align: center;" | '''4.5''' || style="text-align: center;"  colspan="1" | '''2.1''' || style="text-align: center;" | '''2.0'''
 
|}
 
|}
  
Line 483: Line 478:
 
! || Skylake/Kaby Lake || Coffee Lake
 
! || Skylake/Kaby Lake || Coffee Lake
 
|-
 
|-
! Socket || FCLGA-1151 v1 || FCLGA-1151 v2
+
! Socket || FCLGA-1151 || FCLGA-1151
 
|-
 
|-
 
| Contacts || 1151 || 1151
 
| Contacts || 1151 || 1151
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== Die ==
 
== Die ==
Coffee Lake desktop and mobile come in 4, 6, and 8 cores. Each variant has its own die. The major components of the die are:
+
Coffee Lake desktop and mobile come and 4 and 6 cores. Each variant has its own die. The major components of the die are:
  
 
* System Agent
 
* System Agent
Line 543: Line 538:
 
* 11 metal layers
 
* 11 metal layers
 
* 126 mm² die size
 
* 126 mm² die size
* 4 CPU cores + 24 GPU EUs
+
* 4 CPU cores + 23 GPU EUs
  
 
=== Hexa-Core ===
 
=== Hexa-Core ===
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: [[File:coffee lake die (hexa core).png|class=wikichip_ogimage|650px]]
+
: [[File:coffee lake die (hexa core).png|650px]]
  
  
 
: [[File:coffee lake die (hexa core) (annotated).png|650px]]
 
: [[File:coffee lake die (hexa core) (annotated).png|650px]]
 
=== Octa-Core ===
 
* [[14 nm process|14 nm++ process]]
 
* 11 metal layers
 
* ~174 mm² die size
 
* 8 CPU cores + 24 GPU EUs
 
 
: [[File:coffee lake die (octa core).png|800px]]
 
 
 
: [[File:coffee lake die (octa core) (annotated).png|800px]]
 
  
 
=== Additional Shots ===
 
=== Additional Shots ===
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<gallery mode=slideshow>
 
<gallery mode=slideshow>
File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core 6-core processor dies.
+
File:coffee lake wafer.png|Coffee Lake silicon [[wafer]] with 8th generation core processor dies.
File:coffee lake r wafer.png|Coffee Lake Refresh silicon [[wafer]] with 9th generation core 8-core processor dies.
 
 
</gallery>
 
</gallery>
  
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== Documents ==
 
== Documents ==
=== 8th Gen ===
 
 
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
 
* [[:File:8th-gen-intel-core-product-overview.pdf|8th generation Core family product overview]]
 
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]]
 
* [[:File:8th-gen-intel-core-overview.pdf|8th generation Core product overview]]
 
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]]
 
* [[:File:8th-gen-intel-core-product-brief.pdf|8th generation core product brief]]
 
* [[:File:8th-gen-intel-core-lineup-press-deck.pdf|8th generation core lineup]]
 
* [[:File:8th-gen-intel-core-lineup-press-deck.pdf|8th generation core lineup]]
=== 9th Gen ===
 
* [[:File:9th-gen-core-desktop-brief.pdf|9th generation core product brief]]
 
  
 
== References ==
 
== References ==
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Intel 8th Generation Core announcement, Sept 25, 2017.
 
* Intel 8th Generation Core announcement, Sept 25, 2017.

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codenameCoffee Lake +
designerIntel +
first launchedOctober 5, 2017 +
full page nameintel/microarchitectures/coffee lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel + and dell +
microarchitecture typeCPU +
nameCoffee Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +