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Latest revision | Your text | ||
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|l3 per=core | |l3 per=core | ||
|l3 desc=Up to 16-way set associative | |l3 desc=Up to 16-way set associative | ||
− | |core name 2=Cannon Lake | + | |core name=Cannon Lake Y |
+ | |core name 2=Cannon Lake U | ||
|predecessor=Kaby Lake | |predecessor=Kaby Lake | ||
|predecessor link=intel/microarchitectures/kaby lake | |predecessor link=intel/microarchitectures/kaby lake | ||
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== Codenames == | == Codenames == | ||
+ | {{future information}} | ||
+ | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
! Core !! Abbrev !! Description !! Graphics !! Target | ! Core !! Abbrev !! Description !! Graphics !! Target | ||
+ | |- | ||
+ | | {{intel|Cannon Lake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks | ||
|- | |- | ||
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | | {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | ||
+ | |- | ||
+ | | {{intel|Cannon Lake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations | ||
+ | |- | ||
+ | | {{intel|Cannon Lake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis | ||
+ | |- | ||
+ | | {{intel|Cannon Lake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers | ||
|} | |} | ||
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 | + | | rowspan="2" | {{intel|Cannon Lake Y|Y|l=core}}, {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6 |
|- | |- | ||
| colspan="4" | Family 6 Model 102 | | colspan="4" | Family 6 Model 102 | ||
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== Architecture == | == Architecture == | ||
− | === Key changes from {{\\ | + | {{empty section}} |
+ | === Key changes from {{\\|Skylake}} === | ||
* [[10 nm process]] (from [[14 nm]]) | * [[10 nm process]] (from [[14 nm]]) | ||
− | |||
− | |||
− | |||
− | |||
* Mainstream chipset | * Mainstream chipset | ||
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}} | ** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}} | ||
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** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}}) | ** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}}) | ||
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}}) | ** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}}) | ||
− | |||
− | |||
− | |||
====New instructions ==== | ====New instructions ==== | ||
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=== Block Diagram === | === Block Diagram === | ||
− | ==== Entire SoC Overview ==== | + | ==== Entire SoC Overview (dual) ==== |
[[File:cannon lake soc block diagram.svg|800px]] | [[File:cannon lake soc block diagram.svg|800px]] | ||
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==== Gen11 Graphics ==== | ==== Gen11 Graphics ==== | ||
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}. | See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}. | ||
+ | |||
+ | === Block Diagram === | ||
+ | |||
+ | ====== Entire SoC Overview (dual) ====== | ||
+ | [[File:cannon lake soc block diagram (dual).svg|800px]] | ||
+ | |||
+ | ==== Individual Core ==== | ||
+ | {{empty section}} | ||
+ | |||
+ | ==== Gen10 ==== | ||
+ | See {{intel|Gen10#Gen10|l=arch}}. | ||
== Die == | == Die == | ||
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created and tagged accordingly. | created and tagged accordingly. | ||
− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23"> |
− | + | <tr class="comptable-header"><th> </th><th colspan="23">Cannon Lake Chips</th></tr> | |
− | + | <tr class="comptable-header"><th> </th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr> | |
− | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]] | + | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr> |
+ | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannon Lake]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?first launched | ||
|?release price | |?release price | ||
− | |? | + | |?microprocessor family |
+ | |?platform | ||
+ | |?core name | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
+ | |?l3$ size | ||
+ | |?l4$ size | ||
|?tdp | |?tdp | ||
|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |?has advanced vector extensions 2 | ||
+ | |?has intel trusted execution technology | ||
+ | |?has transactional synchronization extensions | ||
+ | |?has intel vpro technology | ||
+ | |?has_intel_vt-d_technology | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |searchlabel= |
+ | |sort=microprocessor family, model number | ||
+ | |order=asc,asc | ||
+ | |userparam=25:19 | ||
|mainlabel=- | |mainlabel=- | ||
+ | |limit=100 | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}} | + | {{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannon Lake]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
== References == | == References == | ||
− | |||
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017. | ||
== See also == | == See also == | ||
* AMD's {{amd|Zen|l=arch}} | * AMD's {{amd|Zen|l=arch}} |
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |