From WikiChip
Editing intel/microarchitectures/cannon lake
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 94: | Line 94: | ||
== Process Technology == | == Process Technology == | ||
− | Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is | + | Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell. |
[[Scaling]]: | [[Scaling]]: |
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |