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− | {{intel title|Cannon Lake|arch}} | + | {{intel title|Cannonlake|arch}} |
| {{microarchitecture | | {{microarchitecture |
− | |atype=CPU
| + | | name = Cannonlake |
− | |name=Cannon Lake | + | | manufacturer = Intel |
− | |designer=Intel
| + | | introduction = 2018-2019 |
− | |manufacturer=Intel | + | | phase-out = |
− | |introduction=May 15, 2018 | + | | process = 10 nm |
− | |process=10 nm
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− | |cores=2
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− | |type=Superscalar
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− | |oooe=Yes
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− | |speculative=Yes
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− | |renaming=Yes
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− | |stages min=14
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− | |stages max=19
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− | |decode=5-way?
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− | |isa=x86-64
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− | |extension=MOVBE
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− | |extension 2=MMX
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− | |extension 3=SSE
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− | |extension 4=SSE2
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− | |extension 5=SSE3
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− | |extension 6=SSSE3
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− | |extension 7=SSE4.1
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− | |extension 8=SSE4.2
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− | |extension 9=POPCNT
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− | |extension 10=AVX
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− | |extension 11=AVX2
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− | |extension 12=AES
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− | |extension 13=PCLMUL
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− | |extension 14=FSGSBASE
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− | |extension 15=RDRND
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− | |extension 16=FMA3
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− | |extension 17=F16C
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− | |extension 18=BMI
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− | |extension 19=BMI2
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− | |extension 20=VT-x
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− | |extension 21=VT-d
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− | |extension 22=TXT
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− | |extension 23=TSX
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− | |extension 24=RDSEED
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− | |extension 25=ADCX
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− | |extension 26=PREFETCHW
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− | |extension 27=CLFLUSHOPT
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− | |extension 28=XSAVE
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− | |extension 29=SGX
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− | |extension 30=MPX
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− | |extension 31=AVX-512
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− | |extension 32=AVX-512F
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− | |extension 33=AVX-512CD
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− | |extension 34=AVX-512BW
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− | |extension 35=AVX-512DQ
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− | |extension 36=AVX-512VL
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− | |extension 37=AVX-512IFMA
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− | |extension 38=AVX-512VBMI
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− | |extension 39=SHA
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− | |extension 40=UMIP
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− | |l1i=32 KiB
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− | |l1i per=core
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− | |l1i desc=8-way set associative
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− | |l1d=32 KiB
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− | |l1d per=core
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− | |l1d desc=8-way set associative
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− | |l2=256 KiB
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− | |l2 per=core
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− | |l2 desc=4-way set associative
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− | |l3=2 MiB
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− | |l3 per=core
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− | |l3 desc=Up to 16-way set associative
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− | |core name 2=Cannon Lake Y
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− | |predecessor=Kaby Lake
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− | |predecessor link=intel/microarchitectures/kaby lake
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− | |successor=Ice Lake
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− | |successor link=intel/microarchitectures/ice lake (client)
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− | |contemporary=Coffee Lake
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− | |contemporary link=intel/microarchitectures/coffee lake
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− | |core names=Yes
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− | |succession=Yes
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− | }}
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− | '''Cannon Lake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannon Lake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the second half of [[2018]]. Cannon Lake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
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− | | |
− | For mobile, Cannon Lake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
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− | | |
− | == Codenames ==
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− | {| class="wikitable"
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− | |-
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− | ! Core !! Abbrev !! Description !! Graphics !! Target
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− | |- | |
− | | {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
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− | |} | |
− | | |
− | == Release Dates ==
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− | Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.
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− | | |
− | == Process Technology ==
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− | Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
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− | | |
− | [[Scaling]]:
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− | | |
− | {| class="wikitable"
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− | |-
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− | ! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
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− | |-
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− | | || [[14 nm]] || [[10 nm]] ||
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− | |-
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− | | Fin Pitch || 42 nm || 34 nm || 0.81x
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− | |-
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− | | Fin Width || 8 nm || 7 nm || 0.88x
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− | |-
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− | | Fin Height || 42 nm || 53 nm || 1.24x
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− | |-
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− | | Gate Pitch || 70 nm || 54 nm || 0.77x
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− | |-
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− | | Interconnect Pitch || 52 nm || 36 nm || 0.69x
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− | |-
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− | | Cell Height || 399 nm || 272 nm || 0.68x
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− | |}
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− | | |
− | == Compiler support ==
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− | Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.
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− | {| class="wikitable"
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− | |-
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− | ! Compiler !! Arch-Specific || Arch-Favorable
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− | |-
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− | | [[ICC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
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− | |-
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− | | [[GCC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
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− | |-
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− | | [[LLVM]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
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− | |-
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− | | [[Visual Studio]] || <code>?</code> || <code>?</code>
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− | |}
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− | | |
− | === CPUID ===
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− | {| class="wikitable tc1 tc2 tc3 tc4"
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− | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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− | |-
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− | | rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
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− | |-
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− | | colspan="4" | Family 6 Model 102
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− | |}
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− | | |
− | == Architecture ==
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− | === Key changes from {{\\|Skylake (client)|Skylake}} ===
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− | * [[10 nm process]] (from [[14 nm]])
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− | | |
− | * {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
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− | ** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
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− | | |
− | * Mainstream chipset
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− | ** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
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− | | |
− | * Mobile Processors
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− | ** LPDDR4/LPDDR4X memory support (from LPDDR3)
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− | *** Rates up to 2400 MT/s
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− | | |
− | * {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
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− | * {{intel|Gen10|l=arch}} GPUs
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− | ** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
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− | ** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
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− | | |
− | * New Integration
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− | ** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
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− | | |
− | ====New instructions ====
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− | Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details.
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− | | |
− | === Block Diagram ===
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− | | |
− | ==== Entire SoC Overview ====
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− | [[File:cannon lake soc block diagram.svg|800px]]
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− | | |
− | ==== Individual Core ====
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− | See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}.
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− | | |
− | ==== Gen11 Graphics ====
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− | See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}.
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− | | |
− | == Die ==
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− | === Dual-core ===
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− | * [[10 nm process]]
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− | * [[13 metal layers]]
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− | * ~8.2 mm x ~8.6 mm
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− | * ~70.52 mm² die size
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− | * 2 CPU cores + 40 GPU EUs
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− | | |
− | == All Cannon Lake Chips ==
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− | <!-- NOTE:
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− | This table is generated automatically from the data in the actual articles.
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− | If a microprocessor is missing from the list, an appropriate article for it needs to be
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− | created and tagged accordingly.
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| | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| + | | succession = Yes |
− | -->
| + | | predecessor = Kaby Lake |
− | {{comp table start}}
| + | | predecessor link = intel/microarchitectures/kaby lake |
− | <table class="comptable sortable tc4 tc5 tc6">
| + | | successor = Icelake |
− | {{comp table header|main|7:List of Cannon Lake-based Processors}}
| + | | successor link = intel/microarchitectures/icelake |
− | {{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
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− | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
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− | |?full page name
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− | |?model number
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?thread count
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− | |?tdp
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− | |?base frequency#GHz
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− | |?turbo frequency (1 core)#GHz
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− | |format=template
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− | |template=proc table 3
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− | |userparam=9
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− | |mainlabel=-
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| }} | | }} |
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
| + | '''Cannonlake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]]. |
− | </table>
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− | {{comp table end}} | |
− | | |
− | == References ==
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− | * Some information was obtained directly from Intel.
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− | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
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− | | |
− | == See also ==
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− | * AMD's {{amd|Zen|l=arch}}
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