From WikiChip
Editing intel/microarchitectures/broadwell (client)
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 156: | Line 156: | ||
* FP multiplication instructions has reduced latency (3 cycles, down from 5) | * FP multiplication instructions has reduced latency (3 cycles, down from 5) | ||
** Affects AVX, SSE, and FP instructions | ** Affects AVX, SSE, and FP instructions | ||
− | * {{x86|CLMUL}} instructions are now a single [[ | + | * {{x86|CLMUL}} instructions are now a single [[μop]], improving latency and throughput |
* The second-level TLB (STLB) | * The second-level TLB (STLB) | ||
** Table was enlarged (1,536 entries, up from 1024) | ** Table was enlarged (1,536 entries, up from 1024) |
Facts about "Broadwell - Microarchitectures - Intel"
codename | Broadwell + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 + and 22 + |
designer | Intel + |
first launched | October 2014 + |
full page name | intel/microarchitectures/broadwell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Broadwell + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |