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== High Core count (EP) == | == High Core count (EP) == | ||
* Key Changes from {{\\|Haswell}}: | * Key Changes from {{\\|Haswell}}: | ||
− | ** Up to | + | ** Up to 22 cores (up from 18) |
− | ** Up to | + | ** Up to 44 threads (up from 36) |
− | ** Up to | + | ** Up to 55 MiB [[last level cache|LLC]] (up from 45 MiB) |
** Up to 2400 DDR (from 2133) | ** Up to 2400 DDR (from 2133) | ||
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|[[File:E5 v4 LCC.png|300px]] || [[File:E5 v4 MCC.png|300px]] || [[File:E5 v4 HCC.png|300px]] | |[[File:E5 v4 LCC.png|300px]] || [[File:E5 v4 MCC.png|300px]] || [[File:E5 v4 HCC.png|300px]] | ||
|} | |} | ||
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== Die == | == Die == | ||
− | ===Dual-core === | + | ===Dual-core Broadwell die=== |
* [[14 nm process]] | * [[14 nm process]] | ||
* 13 metal layers | * 13 metal layers | ||
* 1,300,000,000 transistors | * 1,300,000,000 transistors | ||
− | * 82 | + | * 82 mm<sup>2</sup> die size |
* [[2 cores]] | * [[2 cores]] | ||
+ | : [[File:broadwell die (dual-core).jpg|850px]] | ||
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===Dual-core Broadwell with {{intel|Iris Pro}} die=== | ===Dual-core Broadwell with {{intel|Iris Pro}} die=== | ||
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* 13 metal layers | * 13 metal layers | ||
* ? transistors | * ? transistors | ||
− | * | + | * ? mm<sup>2</sup> die size |
* [[4 cores]] | * [[4 cores]] | ||
: [[File:broadwell core i7-5775C die.jpg|650px]] | : [[File:broadwell core i7-5775C die.jpg|650px]] | ||
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===Deca-core Broadwell === | ===Deca-core Broadwell === | ||
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<tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Multiprocessors]] (4-way)</th></tr> | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Multiprocessors]] (4-way)</th></tr> | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::4]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::4]] | ||
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|?full page name | |?full page name | ||
|?model number | |?model number |
Facts about "Broadwell - Microarchitectures - Intel"
codename | Broadwell + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 + and 22 + |
designer | Intel + |
first launched | October 2014 + |
full page name | intel/microarchitectures/broadwell (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Broadwell + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |