Editing intel/microarchitectures/broadwell (client)

{{intel title|Broadwell|arch}}
{{microarchitecture
| name             = Broadwell
| designer         = Intel
| manufacturer     = Intel
| introduction     = October, 2014
| phase-out        = 
| process          = 14 nm
| cores            = 2
| cores 2          = 4
| cores 3          = 6
| cores 4          = 8
| cores 5          = 16
| cores 6          = 32

| pipeline         = Yes
| type             = Superscalar
| OoOE             = Yes
| speculative      = Yes
| renaming         = Yes
| isa              = IA-32
| isa 2            = x86-64
| stages min       = 14
| stages max       = 19
| issues           = 4

| inst             = Yes
| feature          = 
| extension        = MOVBE
| extension 2      = MMX
| extension 3      = SSE
| extension 4      = SSE2
| extension 5      = SSE3
| extension 6      = SSSE3
| extension 7      = SSE4.1
| extension 8      = SSE4.2
| extension 9      = POPCNT
| extension 10     = AVX
| extension 11     = AVX2
| extension 12     = AES
| extension 13     = PCLMUL
| extension 14     = FSGSBASE
| extension 15     = RDRND
| extension 16     = FMA3
| extension 17     = F16C
| extension 18     = BMI
| extension 19     = BMI2
| extension 20     = VT-x
| extension 21     = VT-d
| extension 22     = TXT
| extension 23     = TSX
| extension 24     = RDSEED
| extension 25     = ADCX
| extension 26     = PREFETCHW

| cache            = Yes
| l1i              = 32 KB
| l1i per          = core
| l1i desc         = 8-way set associative
| l1d              = 32 KB
| l1d per          = core
| l1d desc         = 8-way set associative
| l2               = 256 KB
| l2 per           = core
| l2 desc          = 8-way set associative
| l3               = 1.5 MB
| l3 per           = core
| l3 desc          = 
| l4               = 128 MB
| l4 per           = package
| l4 desc          = on Iris Pro GPUs only

| core names       = Yes
| core name        = Broadwell Y
| core name 2      = Broadwell U
| core name 3      = Broadwell H
| core name 4      = Broadwell DT
| core name 5      = Broadwell EP
| core name 6      = Broadwell EX
| core name 7      = Broadwell E

| succession       = Yes
| predecessor      = Haswell
| predecessor link = intel/microarchitectures/haswell
| successor        = Skylake
| successor link   = intel/microarchitectures/skylake
}}
'''Broadwell''' ('''BDW''') is [[Intel]]'s  [[microarchitecture]] based on the [[14 nm process]] for mobile, desktops, and servers. Introduced in early 2015, Broadwell is a [[process shrink]] of {{\\|Haswell}} which introduced several enhancements. Broadwell is named after [[wikipedia:Broadwell, Illinois|Broadwell, Illinois]].

For desktop and mobile, Broadwell is branded as 5th Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v4}}, {{intel|Xeon E5|Xeon E5 v4}}, and {{intel|Xeon E7|Xeon E7 v4}}.
== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Target
|-
| Broadwell Y || BDW-Y || {{intel|Core M|Core M family}}, SoC for Smartphones, 2-in-1s Tablets, and notebooks
|-
| Broadwell U || BDW-U || {{intel|Core}} ultrabooks
|-
| Broadwell H || BDW-H || IoT (QM87, HM86/HM87 Chipsets), All-in-ones
|-
| Broadwell DT || BDW-DT || Unlocked desktop MPUs
|-
| Broadwell EP || BDW-EP || {{intel|Xeon E5}}, Dual-Processor platform
|-
| Broadwell EX || BDW-EX || {{intel|Xeon E5}}, Multi-Processor platform, QPI
|-
| Broadwell E || BDW-E || High-End Desktops (HEDT)
|}

== Process Technology ==
Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at .0588 um<sup>2</sup>.

Scaling:

[[File:intel 14nm gate.png|215px|left]]
{| class="wikitable"
|-
! !! Haswell !! Broadwell !! 
|-
| || [[22 nm]] || [[14 nm]] ||
|-
| Fin Pitch || 60 nm || 42 nm || 0.70x
|-
| Gate Pitch || 90 nm || 70 nm || 0.78x
|-
| Interconnect Pitch || 80 nm || 52 nm || 0.65x
|}
{{clear}}

== Architecture==
Broadwell is for the most part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions.

=== Key changes from {{\\|Haswell}} ===
* ~5% IPC improvement
* FP multiplication instructions has reduced latency (3 cycles, down from 5)
** Affects AVX, SSE, and FP instructions
* {{x86|CLMUL}} instructions are now a single [[μop]], improving latency and throughput
* The second-level TLB (STLB)
** Table was enlarged (1,536 entries, up from 1024)
** 1GB page mode (16 entries, 4-ways set associative)
* Execution Engine
** Larger scheduler (64 entries, up from 60)
** Larger instruction queue (25 entries/thread, up from 20)
** Faster store-to-load forwarding
** Address prediction for branches and returns was improved
** Improved cryptography acceleration instructions

Core features maintained a 2:1 ratio of performance:power.

==== Graphics ====
* 50% higher sampler throughput
* Improvements for increased geometry, Z, Pixel Fill
* Direct X 11.2, OpenGL 4.3
* OpenCL 1.2 and 2.0 (with Shared Virtual Memory)
* Up to 24 EUs (20% addition, up from 20 in {{\\|Haswell}}), 48 EUs on {{intel|Iris Pro Graphics}}

==== New instructions ====
{{main|#Added instructions|l1=See #Added_instructions for the complete list}}
Broadwell introduced a number of new instructions:
* {{x86|RDSEED|<code>RDSEED</code>}} - Generates 16, 32 or 64 bit random numbers seeds ([[NIST SP 800-90B]] & [[NIST SP 800-90C]])
* {{x86|ADCX|<code>ADCX</code>}} - Arbitrary precision integer operations 
* {{x86|PREFETCHW|<code>PREFETCHW</code>}} - Prefetch data into caches, hinting a write is expected in the future

=== Block Diagram ===
[[File:broadwell block diagram.svg]]

=== Memory Hierarchy ===
* Cache
** L1 Cache:
*** 32 KB 8-way [[set associative]] instruction, 64 B line size
*** 32 KB 8-way set associative data, 64 B line size
*** Write-back policy
*** Per core
** L2 Cache:
*** 256 KB 8-way set associative, 64 B line size
*** Write-back policy
*** Per core
** L3 Cache:
*** 1.5 - 3 MB per core, 64 B line size
*** 16-20 -way set associative
*** Write-back policy
** L4 Cache:
*** 128 MB
*** [[eDRAM]]
*** shared with GPU ({{intel|Crystal Well}})
*** {{intel|Iris Pro}} models only

Broadwell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.
* TLBs:
** ITLB
*** 4KB page translations:
**** 128 entries; 4-way set associative
**** dynamic partition; divided between the two threads
*** 2MB/4MB page translations:
**** 8 entries; fully associative
**** Duplicated for each thread
** DTLB
*** 4KB page translations:
**** 64 entries; 4-way set associative
**** fixed partition; divided between the two threads
*** 2MB/4MB page translations:
**** 32 entries; 4-way set associative
*** 1G page translations:
**** 4 entries; 4-way set associative
** STLB
*** 4KB+2M page translations:
**** 1536 entries; 6-way set associative
**** shared
*** 1GB page translations:
**** 16 entries; 4-way set associative

=== Pipeline ===
{{main|intel/microarchitectures/haswell#Pipeline|l1=Haswell's Pipeline}}
Broadwell's pipeline is identical to Haswell.

== Die ==
===Dual-core Broadwell die===

: [[File:broadwell die (dual-core).jpg|850px]]

* 1,300,000,000 transistors
* 82 mm<sup>2</sup>


===Dual-core Broadwell with {{intel|Iris Pro}} die===

: [[File:broadwell with iris pro die (dual-core).png|850px]]

===Deca-core Broadwell ===

* {{intel|Core i7-6950X}}
* Deca-core microprocessor
* 3,400,000,000 transistors
* 246 mm<sup>2</sup>

:[[File:broadwell (deca-core) die shot.png|650px]]

:[[File:broadwell (deca-core) die shot (annotated).png|650px]]

== Added instructions ==
'''{{x86|RDSEED}}''' - Generates 16, 32 or 64 bit random numbers seeds (both [[NIST SP 800-90B]] and [[NIST SP 800-90C]] compliant)

{{collist
| count = 1
| width = 150px
|
* {{x86|RDSEED}}
}}

'''{{x86|ADCX}}''' - Arbitrary precision integer operations

{{collist
| count = 1
| width = 150px
|
* {{x86|ADCX}}
* {{x86|ADOX}}
}}

'''{{x86|PREFETCHW}}''' - Prefetch data into caches, hinting a write is expected in the future.

{{collist
| count = 1
| width = 150px
|
* {{x86|PREFETCHW}}
}}

== Cores ==
{{empty section}}

== All Broadwell Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
<table class="wikitable sortable">
<tr><th colspan="12" style="background:#D6D6FF;">Broadwell Chips</th></tr>
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
<tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
{{#ask: [[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Broadwell]]
 |?full page name
 |?model number
 |?microarchitecture
 |?platform
 |?core name
 |?first launched
 |?sdp
 |?tdp
 |?base frequency
 |?max memory
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 2
 |userparam=13
 |mainlabel=-
}}
<tr><th colspan="12">Count: {{#ask:[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Broadwell]]|format=count}}</th></tr>
</table>
codename	Broadwell +
core count	2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 + and 22 +
designer	Intel +
first launched	October 2014 +
full page name	intel/microarchitectures/broadwell (client) +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Broadwell +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +