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| | {{intel title|Broadwell|arch}} | | {{intel title|Broadwell|arch}} |
| | {{microarchitecture | | {{microarchitecture |
| − | |atype=CPU
| + | | name = Broadwell |
| − | |name=Broadwell | + | | manufacturer = Intel |
| − | |designer=Intel
| + | | introduction = October, 2014 |
| − | |manufacturer=Intel | + | | phase-out = |
| − | |introduction=October, 2014 | + | | process = 14 nm |
| − | |process=14 nm | + | | cores = 2 |
| − | |cores=2 | + | | cores 2 = 4 |
| − | |cores 2=4 | + | | cores 3 = 6 |
| − | |cores 3=6 | + | | cores 4 = 8 |
| − | |cores 4=8 | + | | cores 5 = 16 |
| − | |cores 5=10 | + | | cores 6 = 32 |
| − | |cores 6=12 | + | |
| − | |cores 7=14
| + | | pipeline = Yes |
| − | |cores 8=16 | + | | type = Superscalar |
| − | |cores 9=18 | + | | OoOE = Yes |
| − | |cores 10=20 | + | | speculative = Yes |
| − | |cores 11=22
| + | | renaming = Yes |
| − | |type=Superscalar
| + | | isa = IA-32 |
| − | |speculative=Yes | + | | isa 2 = x86-64 |
| − | |renaming=Yes | + | | stages min = 14 |
| − | |stages min=14 | + | | stages max = 19 |
| − | |stages max=19
| + | | issues = 4 |
| − | |isa=x86-64 | |
| − | |extension=MOVBE | |
| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4.1
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| − | |extension 8=SSE4.2
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| − | |extension 9=POPCNT
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| − | |extension 10=AVX
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| − | |extension 11=AVX2
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| − | |extension 12=AES
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| − | |extension 13=PCLMUL
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| − | |extension 14=FSGSBASE
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| − | |extension 15=RDRND | |
| − | |extension 16=FMA3
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| − | |extension 17=F16C
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| − | |extension 18=BMI
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| − | |extension 19=BMI2
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| − | |extension 20=VT-x
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| − | |extension 21=VT-d
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| − | |extension 22=TXT
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| − | |extension 23=TSX
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| − | |extension 24=RDSEED
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| − | |extension 25=ADCX
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| − | |extension 26=PREFETCHW
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| − | |l1i=32 KiB
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| − | |l1i per=core
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| − | |l1i desc=8-way set associative
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| − | |l1d=32 KiB
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| − | |l1d per=core
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| − | |l1d desc=8-way set associative
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| − | |l2=256 KiB
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| − | |l2 per=core
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| − | |l2 desc=8-way set associative
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| − | |l3=1.5 MiB
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| − | |l3 per=core
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| − | |l4=128 MiB
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| − | |l4 per=package
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| − | |l4 desc=on Iris Pro GPUs only
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| − | |core name=Broadwell Y
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| − | |core name 2=Broadwell U
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| − | |core name 3=Broadwell H
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| − | |core name 4=Broadwell DT
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| − | |core name 5=Broadwell EP
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| − | |core name 6=Broadwell EX
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| − | |core name 7=Broadwell E
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| − | |predecessor=Haswell
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| − | |predecessor link=intel/microarchitectures/haswell
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| − | |successor=Skylake (client)
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| − | |successor link=intel/microarchitectures/skylake (client)
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| − | |successor 2=Skylake (server)
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| − | |successor 2 link=intel/microarchitectures/skylake (server)
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| − | |pipeline=Yes
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| − | |OoOE=Yes
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| − | |issues=4 | |
| − | |inst=Yes
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| − | |cache=Yes
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| − | |core names=Yes
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| − | |succession=Yes
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| − | }}
| |
| − | '''Broadwell''' ('''BDW''') is [[Intel]]'s [[microarchitecture]] based on the [[14 nm process]] for mobile, desktops, and servers. Introduced in early 2015, Broadwell is a [[process shrink]] of {{\\|Haswell}} which introduced several enhancements. Broadwell is named after [[wikipedia:Broadwell, Illinois|Broadwell, Illinois]].
| |
| | | | |
| − | For desktop and mobile, Broadwell is branded as 5th Generation Intel {{intel|Core}} processors. For server class processors, Intel branded it as {{intel|Xeon E3|Xeon E3 v4}}, {{intel|Xeon E5|Xeon E5 v4}}, and {{intel|Xeon E7|Xeon E7 v4}}.
| + | | inst = Yes |
| − | == Codenames ==
| + | | feature = |
| − | {| class="wikitable"
| + | | extension = MOVBE |
| − | |- | + | | extension 2 = MMX |
| − | ! Core !! Abbrev !! Target
| + | | extension 3 = SSE |
| − | |- | + | | extension 4 = SSE2 |
| − | | Broadwell Y || BDW-Y || {{intel|Core M|Core M family}}, SoC for Smartphones, 2-in-1s Tablets, and notebooks | + | | extension 5 = SSE3 |
| − | |- | + | | extension 6 = SSSE3 |
| − | | Broadwell U || BDW-U || {{intel|Core}} ultrabooks | + | | extension 7 = SSE4.1 |
| − | |- | + | | extension 8 = SSE4.2 |
| − | | Broadwell H || BDW-H || IoT (QM87, HM86/HM87 Chipsets), All-in-ones | + | | extension 9 = POPCNT |
| − | |- | + | | extension 10 = AVX |
| − | | Broadwell DT || BDW-DT || Unlocked desktop MPUs | + | | extension 11 = AVX2 |
| − | |- | + | | extension 12 = AES |
| − | | Broadwell EP || BDW-EP || {{intel|Xeon E5}}, Dual-Processor platform | + | | extension 13 = PCLMUL |
| − | |- | + | | extension 14 = FSGSBASE |
| − | | Broadwell EX || BDW-EX || {{intel|Xeon E7}}, Multi-Processor platform, QPI | + | | extension 15 = RDRND |
| − | |- | + | | extension 16 = FMA |
| − | | Broadwell E || BDW-E || High-End Desktops (HEDT) | + | | extension 17 = BMI |
| − | |} | + | | extension 18 = BMI2 |
| | + | | extension 19 = F16C |
| | + | | extension 20 = RDSEED |
| | + | | extension 21 = ADCX |
| | + | | extension 22 = PREFETCHW |
| | | | |
| − | == Process Technology == | + | | cache = Yes |
| − | {| class="wikitable" style="float: right;"
| + | | l1i = 32 KB |
| − | ! colspan="2" | 14 nm Manufacturing Fabs
| + | | l1i per = core |
| − | |- | + | | l1i desc = 8-way set associative |
| − | ! Fab !! Location
| + | | l1d = 32 KB |
| − | |- | + | | l1d per = core |
| − | | D1X || Hillsboro, Oregon | + | | l1d desc = 8-way set associative |
| − | |- | + | | l2 = 256 KB |
| − | | D1D || Hillsboro, Oregon | + | | l2 per = core |
| − | |- | + | | l2 desc = 8-way set associative |
| − | | D1C || Hillsboro, Oregon
| + | | l3 = 1.5 MB |
| − | |- | + | | l3 per = core |
| − | | Fab 32 || Chandler, Arizona | + | | l3 desc = |
| − | |- | |
| − | | Fab 24 || Leixlip, Ireland | |
| − | |}
| |
| − | Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high performance and high density.
| |
| | | | |
| | + | | core names = Yes |
| | + | | core name = Broadwell Y |
| | + | | core name 2 = Broadwell U |
| | + | | core name 3 = Broadwell H |
| | + | | core name 4 = Broadwell DT |
| | + | | core name 5 = Broadwell EP |
| | + | | core name 6 = Broadwell EX |
| | + | | core name 7 = Broadwell E |
| | | | |
| − | [[Scaling]]: | + | | succession = Yes |
| | + | | predecessor = Haswell |
| | + | | predecessor link = intel/microarchitectures/haswell |
| | + | | successor = Skylake |
| | + | | successor link = intel/microarchitectures/skylake |
| | + | }} |
| | + | '''Broadwell''' is [[Intel]]'s [[microarchitecture]] based on the [[14 nm process]] for mobile, desktops, and servers. Introduced in early 2015, Broadwell is a [[process shrink]] of {{\\|Haswell}} which introduced several enhancements. |
| | | | |
| | + | == Codenames == |
| | {| class="wikitable" | | {| class="wikitable" |
| | |- | | |- |
| − | ! !! Haswell !! Broadwell !! Δ !! rowspan="8" | [[File:intel 14nm fin.png|250px]] | + | ! Core !! Target |
| | |- | | |- |
| − | | || [[22 nm]] || [[14 nm]] || | + | | Broadwell Y || {{intel|Core M|Core M family}}, SoC for Smartphones, 2-in-1s Tablets, and notebooks |
| | |- | | |- |
| − | | Fin Pitch || 60 nm || 42 || 0.70x | + | | Broadwell U || {{intel|Core}} ultrabooks |
| | |- | | |- |
| − | | Fin Width || 8 nm || 8 nm || 1x | + | | Broadwell H || IoT (QM87, HM86/HM87 Chipsets), All-in-ones |
| | |- | | |- |
| − | | Fin Height || 34 nm || 42 nm || 1.24x | + | | Broadwell DT || Unlocked desktop MPUs |
| | |- | | |- |
| − | | Gate Pitch || 90 nm || 70 nm || 0.78x | + | | Broadwell EP || {{intel|Xeon E5}}, Dual-Processor platform |
| | |- | | |- |
| − | | Interconnect Pitch || 80 nm || 52 nm || 0.65x | + | | Broadwell EX || {{intel|Xeon E5}}, Multi-Processor platform, QPI |
| | |- | | |- |
| − | | Cell Height || 840 nm || 399 nm || 0.48x | + | | Broadwell E || High-End Desktops (HEDT) |
| | |} | | |} |
| | | | |
| | == Architecture== | | == Architecture== |
| − | Broadwell is for the most part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions. | + | Broadwell is for the most part identical to {{\\|Haswell}} with server enhancements. |
| | | | |
| | === Key changes from {{\\|Haswell}} === | | === Key changes from {{\\|Haswell}} === |
| − | [[File:broadwell buffer window.png|right|350px]]
| |
| | * ~5% IPC improvement | | * ~5% IPC improvement |
| | * FP multiplication instructions has reduced latency (3 cycles, down from 5) | | * FP multiplication instructions has reduced latency (3 cycles, down from 5) |
| | ** Affects AVX, SSE, and FP instructions | | ** Affects AVX, SSE, and FP instructions |
| − | * {{x86|CLMUL}} instructions are now a single [[µOP]], improving latency and throughput | + | * {{x86|CLMUL}} instructions are now a single [[μop]], improving latency and throughput |
| | * The second-level TLB (STLB) | | * The second-level TLB (STLB) |
| | ** Table was enlarged (1,536 entries, up from 1024) | | ** Table was enlarged (1,536 entries, up from 1024) |
| | ** 1GB page mode (16 entries, 4-ways set associative) | | ** 1GB page mode (16 entries, 4-ways set associative) |
| − | * Execution Engine
| + | * Larger out-of-order scheduler |
| − | ** Larger scheduler (64 entries, up from 60)
| + | * Faster store-to-load forwarding |
| − | ** Larger instruction queue (25 entries/thread, up from 20)
| + | * Address prediction for branches and returns was improved |
| − | ** Faster store-to-load forwarding
| + | * Improved cryptography acceleration instructions |
| − | ** Address prediction for branches and returns was improved
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| − | ** Improved cryptography acceleration instructions
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| | | | |
| | Core features maintained a 2:1 ratio of performance:power. | | Core features maintained a 2:1 ratio of performance:power. |
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| | * OpenCL 1.2 and 2.0 (with Shared Virtual Memory) | | * OpenCL 1.2 and 2.0 (with Shared Virtual Memory) |
| | * Up to 24 EUs (20% addition, up from 20 in {{\\|Haswell}}), 48 EUs on {{intel|Iris Pro Graphics}} | | * Up to 24 EUs (20% addition, up from 20 in {{\\|Haswell}}), 48 EUs on {{intel|Iris Pro Graphics}} |
| − |
| |
| − | ==== New instructions ====
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| − | Broadwell introduced a number of new instructions:
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| − | * {{x86|RDSEED|<code>RDSEED</code>}} - Generates 16, 32 or 64 bit random numbers seeds ([[NIST SP 800-90B]] & [[NIST SP 800-90C]])
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| − | * {{x86|ADCX|<code>ADCX</code>}} - Arbitrary precision integer operations
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| − | * {{x86|PREFETCHW|<code>PREFETCHW</code>}} - Prefetch data into caches, hinting a write is expected in the future
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| − | * {{x86|SMAP|<code>SMAP</code>}} - Supervisor Mode Access Prevention
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| − |
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| − | === Block Diagram ===
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| − | [[File:broadwell block diagram.svg]]
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| − |
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| − | === Memory Hierarchy ===
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| − | [[File:Intel-Xeon-processor-D-1500-wafer.jpg|right|thumb|350px|Broadwell {{intel|Xeon D}} wafer]]
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| − | * Cache
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| − | ** L1 Cache:
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| − | *** 32 KiB 8-way [[set associative]] instruction, 64 B line size
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| − | *** 32 KiB 8-way set associative data, 64 B line size
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| − | *** Write-back policy
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| − | *** Per core
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| − | ** L2 Cache:
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| − | *** 256 KiB 8-way set associative, 64 B line size
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| − | *** Write-back policy
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| − | *** Per core
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| − | ** L3 Cache:
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| − | *** 1.5/2.0/2.5 MiB per core, 64 B line size
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| − | *** 12/16/20 -way set associative
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| − | *** Write-back policy
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| − | ** L4 Cache:
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| − | *** 128 MiB
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| − | *** [[eDRAM]]
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| − | *** shared with GPU ({{intel|Crystal Well}})
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| − | *** {{intel|Iris Pro}} models only
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| − |
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| − | Broadwell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified second level TLB.
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| − | * TLBs:
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| − | ** ITLB
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| − | *** 4 KiB page translations:
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| − | **** 128 entries; 4-way set associative
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| − | **** dynamic partition; divided between the two threads
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| − | *** 2 MiB / 4MiB page translations:
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| − | **** 8 entries; fully associative
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| − | **** Duplicated for each thread
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| − | ** DTLB
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| − | *** 4 KiB page translations:
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| − | **** 64 entries; 4-way set associative
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| − | **** fixed partition; divided between the two threads
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| − | *** 2 MiB / 4 MiB page translations:
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| − | **** 32 entries; 4-way set associative
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| − | *** 1 GiB page translations:
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| − | **** 4 entries; 4-way set associative
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| − | ** STLB
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| − | *** 4 KiB + 2 MiB page translations:
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| − | **** 1536 entries; 6-way set associative
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| − | **** shared
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| − | *** 1 GiB page translations:
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| − | **** 16 entries; 4-way set associative
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| − |
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| − | === Pipeline ===
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| − | {{main|intel/microarchitectures/haswell#Pipeline|l1=Haswell's Pipeline}}
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| − | Broadwell's pipeline is identical to Haswell.
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| − |
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| − | == High Core count (EP) ==
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| − | * Key Changes from {{\\|Haswell}}:
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| − | ** Up to 24 cores (up from 18)
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| − | ** Up to 48 threads (up from 36)
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| − | ** Up to 60 MiB [[last level cache|LLC]] (up from 45 MiB)
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| − | ** Up to 2400 DDR (from 2133)
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| − |
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| − | {{expand section}}
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| − |
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| − | === Snoop Modes ===
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| − | Broadwell EP has four snoop modes: Home Snoop (HS), Early Snoop (ES), Cluster-on-Die (COD) and Home Snoop with Directory and Opportunistic Snoop Broadcast (HS with DIR + OSB).
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| − |
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| − | {| class="wikitable tc2 tc3 tc4 tc5"
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| − | |-
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| − | ! Performance Metric !! HS \w DIR+OSB !! COD !! Home Snoop !! Early Snoop
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| − | |-
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| − | ! colspan="5" | System configured as [[NUMA]]
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| − | |-
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| − | | LCC Hit Latency || Low || Lowest || Low || Low
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| − | |-
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| − | | Local Memory Latency || Low || Lowest || High<sup>1</sup> || Medium<sup>1</sup>
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| − | |-
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| − | | Remote Memory Latency || Low || Low-High<sup>1</sup> || Low || Lowest
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| − | |-
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| − | | Local Memory Bandwidth || High || High || High || Low
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| − | |-
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| − | | Remote Memory Bandwidth || High || Medium || High || Medium
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| − | |-
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| − | ! colspan="5" | System configured as [[UMA]]
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| − | |-
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| − | | Memory Latency || Low || rowspan="2" | Not an advised configuration || Low || Lowest
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| − | |-
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| − | | Memory Bandwidth || High || High || Medium
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| − | |}
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| − |
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| − | <sup>1</sup> - Performance depends on the directory state. Expect low latency with a clean directory and high latency with a dirty directory.
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| − |
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| − | === Die Stats ===
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="3" style="background:#D6D6FF;" | Layout
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| − | |-
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| − | ! Low Core Count (LCC) !! Medium Core Count (MCC) !! High Core Count (HCC)
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| − | |-
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| − | | Up to 10 Cores || 12-14 Cores || 16-24 Cores
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| − | |-
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| − | | 246.24 mm² || 306.18 mm² || 456.12 mm²
| |
| − | |-
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| − | | ~3,200,000,000 Transistors || ~4,700,000,000 Transistors || ~7,200,000,000 Transistors
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| − | |-
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| − | |[[File:E5 v4 LCC.png|300px]] || [[File:E5 v4 MCC.png|300px]] || [[File:E5 v4 HCC.png|300px]]
| |
| − | |}
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| − |
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| − | == Die ==
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| − | ===Dual-core ===
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| − |
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| − | * [[14 nm process]]
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| − | * 13 metal layers
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| − | * 1,300,000,000 transistors
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| − | * 82 mm² die size
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| − | * [[2 cores]]
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| − |
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| − |
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| − | : [[File:broadwell die (dual-core).png|850px]]
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| − |
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| − |
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| − | : [[File:broadwell die (dual-core, 2).png|850px]]
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| − |
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| − | ===Dual-core Broadwell with {{intel|Iris Pro}} die===
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| − |
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| − | * [[14 nm process]]
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| − | * 13 metal layers
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| − | * 1,900,000,000 transistors
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| − | * 133 mm<sup>2</sup> die size
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| − | * [[2 cores]]
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| − |
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| − | : [[File:broadwell with iris pro die (dual-core).png|850px]]
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| − |
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| − |
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| − | ===Quad-core Broadwell with {{intel|Iris Pro}} die===
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| − |
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| − | Die shot of the {{intel|Core i7-5775C}} microprocessor.
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| − |
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| − | * [[14 nm process]]
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| − | * 13 metal layers
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| − | * ? transistors
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| − | * 182 mm<sup>2</sup> die size
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| − | * [[4 cores]]
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| − |
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| − | : [[File:broadwell core i7-5775C die.jpg|650px]]
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| − |
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| − | ===Deca-core Broadwell ===
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| − |
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| − | Die shot of the {{intel|Core i7-6950X}} microprocessor.
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| − |
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| − | * [[14 nm process]]
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| − | * ? metal layers
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| − | * 3,400,000,000 transistors
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| − | * 246 mm<sup>2</sup> die size
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| − | * [[10 cores]]
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| − |
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| − | :[[File:broadwell (deca-core) die shot.png|650px]]
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| − |
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| − | :[[File:broadwell (deca-core) die shot (annotated).png|650px]]
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| − |
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| − | == Added instructions ==
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| − | '''{{x86|RDSEED}}''' - Generates 16, 32 or 64 bit random numbers seeds (both [[NIST SP 800-90B]] and [[NIST SP 800-90C]] compliant)
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| − |
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| − | {{collist
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| − | | count = 1
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| − | | width = 150px
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| − | |
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| − | * {{x86|RDSEED}}
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| − | }}
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| − |
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| − | '''{{x86|ADCX}}''' - Arbitrary precision integer operations
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| − |
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| − | {{collist
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| − | | count = 1
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| − | | width = 150px
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| − | |
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| − | * {{x86|ADCX}}
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| − | * {{x86|ADOX}}
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| − | }}
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| − |
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| − | '''{{x86|PREFETCHW}}''' - Prefetch data into caches, hinting a write is expected in the future.
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| − |
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| − | {{collist
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| − | | count = 1
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| − | | width = 150px
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| − | |
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| − | * {{x86|PREFETCHW}}
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| − | }}
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| − |
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| − | == Cores ==
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| − | {{empty section}}
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| − |
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| − | == All Broadwell Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc6 tc7 tc20 tc21 tc22 tc23 tc24 tc25">
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| − | <tr class="comptable-header"><th> </th><th colspan="19">List of Broadwell Processors</th></tr>
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| − | <tr class="comptable-header"><th> </th><th colspan="9">Main processor</th><th colspan="5">{{intel|Turbo Boost}}</th><th>Mem</th><th colspan="3">IGP</th></tr>
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| − | {{comp table header 1|cols=Launched, Price, Family, Core Name, Cores, Threads, %L2$, %L3$, TDP, %Frequency, 1 Core, 2 Cores, 3 Cores, 4 Cores, Max Mem, GPU, %Frequency, Turbo}}
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| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Uniprocessors]]</th></tr>
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| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::1]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core name
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| − | |?core count
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| − | |?thread count
| |
| − | |?l2$ size
| |
| − | |?l3$ size
| |
| − | |?tdp
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency (1 core)#GHz
| |
| − | |?turbo frequency (2 cores)#GHz
| |
| − | |?turbo frequency (3 cores)#GHz
| |
| − | |?turbo frequency (4 cores)#GHz
| |
| − | |?max memory#GiB
| |
| − | |?integrated gpu
| |
| − | |?integrated gpu base frequency
| |
| − | |?integrated gpu max frequency
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |searchlabel=
| |
| − | |sort=microprocessor family, model number
| |
| − | |order=asc,asc
| |
| − | |userparam=20
| |
| − | |mainlabel=-
| |
| − | |limit=200
| |
| − | }}
| |
| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Multiprocessors]] (2-way)</th></tr>
| |
| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::2]]
| |
| − | |?full page name
| |
| − | |?model number
| |
| − | |?first launched
| |
| − | |?release price
| |
| − | |?microprocessor family
| |
| − | |?core name
| |
| − | |?core count
| |
| − | |?thread count
| |
| − | |?l2$ size
| |
| − | |?l3$ size
| |
| − | |?tdp
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency (1 core)#GHz
| |
| − | |?turbo frequency (2 cores)#GHz
| |
| − | |?turbo frequency (3 cores)#GHz
| |
| − | |?turbo frequency (4 cores)#GHz
| |
| − | |?max memory#GiB
| |
| − | |?integrated gpu
| |
| − | |?integrated gpu base frequency
| |
| − | |?integrated gpu max frequency
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |searchlabel=
| |
| − | |sort=microprocessor family, model number
| |
| − | |order=asc,asc
| |
| − | |userparam=20
| |
| − | |mainlabel=-
| |
| − | |limit=200
| |
| − | }}
| |
| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Multiprocessors]] (4-way)</th></tr>
| |
| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::4]]
| |
| − | |?full page name
| |
| − | |?model number
| |
| − | |?first launched
| |
| − | |?release price
| |
| − | |?microprocessor family
| |
| − | |?core name
| |
| − | |?core count
| |
| − | |?thread count
| |
| − | |?l2$ size
| |
| − | |?l3$ size
| |
| − | |?tdp
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency (1 core)#GHz
| |
| − | |?turbo frequency (2 cores)#GHz
| |
| − | |?turbo frequency (3 cores)#GHz
| |
| − | |?turbo frequency (4 cores)#GHz
| |
| − | |?max memory#GiB
| |
| − | |?integrated gpu
| |
| − | |?integrated gpu base frequency
| |
| − | |?integrated gpu max frequency
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |searchlabel=
| |
| − | |sort=microprocessor family, model number
| |
| − | |order=asc,asc
| |
| − | |userparam=20
| |
| − | |mainlabel=-
| |
| − | |limit=200
| |
| − | }}
| |
| − | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="20">[[Multiprocessors]] (8-way)</th></tr>
| |
| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::8]]
| |
| − | |?full page name
| |
| − | |?model number
| |
| − | |?first launched
| |
| − | |?release price
| |
| − | |?microprocessor family
| |
| − | |?core name
| |
| − | |?core count
| |
| − | |?thread count
| |
| − | |?l2$ size
| |
| − | |?l3$ size
| |
| − | |?tdp
| |
| − | |?base frequency#GHz
| |
| − | |?turbo frequency (1 core)#GHz
| |
| − | |?turbo frequency (2 cores)#GHz
| |
| − | |?turbo frequency (3 cores)#GHz
| |
| − | |?turbo frequency (4 cores)#GHz
| |
| − | |?max memory#GiB
| |
| − | |?integrated gpu
| |
| − | |?integrated gpu base frequency
| |
| − | |?integrated gpu max frequency
| |
| − | |format=template
| |
| − | |template=proc table 3
| |
| − | |searchlabel=
| |
| − | |sort=microprocessor family, model number
| |
| − | |order=asc,asc
| |
| − | |userparam=20
| |
| − | |mainlabel=-
| |
| − | |limit=200
| |
| − | }}
| |
| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]]}}
| |
| − | </table>
| |
| − | {{comp table end}}
| |
