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{{intel title|Bonnell|arch}} | {{intel title|Bonnell|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |atype=CPU | + | | atype = CPU |
− | |name=Bonnell | + | | name = Bonnell |
− | |designer=Intel | + | | designer = Intel |
− | |manufacturer=Intel | + | | manufacturer = Intel |
− | |introduction=March 2, 2008 | + | | introduction = March 2, 2008 |
− | |phase-out=2011 | + | | phase-out = 2011 |
− | |process=45 nm | + | | process = 45 nm |
− | |cores=1 | + | | cores = 1 |
− | |cores 2=2 | + | | cores 2 = 2 |
− | |type=Superscalar | + | |
− | | | + | | pipeline = Yes |
− | |speculative= | + | | type = Superscalar |
− | |renaming=No | + | | OoOE = No |
− | + | | speculative = No | |
− | + | | renaming = No | |
|isa=x86-64 | |isa=x86-64 | ||
− | |extension=MOVBE | + | | stages min = 16 |
− | |extension 2=MMX | + | | stages max = 19 |
− | |extension 3=SSE | + | | issues = 2 |
− | |extension 4=SSE2 | + | |
− | |extension 5=SSE3 | + | | inst = Yes |
− | |extension 6=SSSE3 | + | | feature = |
− | |l1i=32 KiB | + | | extension = MOVBE |
− | |l1i per=Core | + | | extension 2 = MMX |
− | |l1i desc=8-way set associative | + | | extension 3 = SSE |
− | |l1d=24 KiB | + | | extension 4 = SSE2 |
− | |l1d per=Core | + | | extension 5 = SSE3 |
− | |l1d desc=6-way set associative | + | | extension 6 = SSSE3 |
− | |l2=512 KiB | + | |
− | |l2 per=Core | + | | cache = Yes |
− | |l2 desc=8-way set associative | + | | l1i = 32 KiB |
− | |core name=Silverthorne | + | | l1i per = Core |
− | |core name 2=Diamondville | + | | l1i desc = 8-way set associative |
− | |core name 3=Lincroft | + | | l1d = 24 KiB |
− | |core name 4=Pineview | + | | l1d per = Core |
− | |core name 5=Tunnel Creek | + | | l1d desc = 6-way set associative |
− | |core name 6=Stellarton | + | | l2 = 512 KiB |
− | |core name 7=Sodaville | + | | l2 per = Core |
− | |core name 8=Groveland | + | | l2 desc = 8-way set associative |
− | |successor=Saltwell | + | |
− | |successor link=intel/microarchitectures/saltwell | + | | core names = Yes |
− | + | | core name = Silverthorne | |
− | + | | core name 2 = Diamondville | |
− | + | | core name 3 = Lincroft | |
− | + | | core name 4 = Pineview | |
− | + | | core name 5 = Tunnel Creek | |
− | + | | core name 6 = Stellarton | |
− | + | | core name 7 = Sodaville | |
+ | | core name 8 = Groveland | ||
+ | |||
+ | | succession = Yes | ||
+ | | predecessor = | ||
+ | | successor = Saltwell | ||
+ | | successor link = intel/microarchitectures/saltwell | ||
}} | }} | ||
'''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low voltage [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. | '''Bonnell''' was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low voltage [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonnell, which was named after the highest point in [[wikipedia:Austin, Texas|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |