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Bonnell has two [[address generation units]] (AGUs). For data, there is 24 [[KiB]] [[write-back]] L1 cache with a 2-level DTLB hierarchy, hardware page walker, and an integer store-to-load forwarding support. Additionally, there is a rather large 512 KiB [[L2 cache]] with inline ECC and [[hardware pre-fetchers]]. The tag, [[Least Recently Used|LRU]], and the state bits are all stored in a single array to minimize area. The tag and data consist of 8 4.5 KiB tag sub arrays and 32 17.5 KiB data sub-arrays made of 256 cells on the bit line and 136 cells on the write line. | Bonnell has two [[address generation units]] (AGUs). For data, there is 24 [[KiB]] [[write-back]] L1 cache with a 2-level DTLB hierarchy, hardware page walker, and an integer store-to-load forwarding support. Additionally, there is a rather large 512 KiB [[L2 cache]] with inline ECC and [[hardware pre-fetchers]]. The tag, [[Least Recently Used|LRU]], and the state bits are all stored in a single array to minimize area. The tag and data consist of 8 4.5 KiB tag sub arrays and 32 17.5 KiB data sub-arrays made of 256 cells on the bit line and 136 cells on the write line. | ||
− | As a power-saving feature, the L2 cache can be configured down to 2-way dynamically | + | As a power-saving feature, the L2 cache can be configured down to 2-way dynamically. Additionally, for less demanding tasks, the Bonnell power gates unused ways. It's interesting to note that the design team placed the TAG blocks at the bottom of the DATA arrays allowing, in theory, to expend the L2 to 1 MiB should they want to. |
=== I/O Bus === | === I/O Bus === |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |