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+ | === Branch Prediction === | ||
+ | * [[Two-level adaptive predictor]] | ||
+ | * 12-bit branch history register | ||
+ | * Pattern history table has 4096 entries (shared between threads) | ||
+ | * Branch buffer target has 128 entries (4-way, 32 sets) | ||
+ | * Unconditional jumps are ignored | ||
+ | * Always-taken and never-taken are marked in the table | ||
+ | * Penalties: | ||
+ | ** 13 stages for miss prediction | ||
+ | ** 7 stages for correct prediction but missing [[branch target buffer]] (BTB) | ||
== Die == | == Die == |
Facts about "Bonnell - Microarchitectures - Intel"
codename | Bonnell + |
core count | 1 + and 2 + |
designer | Intel + |
first launched | March 2, 2008 + |
full page name | intel/microarchitectures/bonnell + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Bonnell + |
phase-out | 2011 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 16 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |