Editing intel/cores/skylake u

{{intel title|Skylake U|core}}
{{core
| name              = Skylake U
| image             = skylake u (front; iris).png
| image size        = 250px
| caption           = 3-die config Iris Plus SKL-U (with OPC)
| image 2           = skylake u (front; standard).png
| image 2 size      = 250px
| caption 2         = 2-die config SKL-U
| developer         = Intel
| manufacturer      = Intel
| first announced   = September 1, 2015
| first launched    = September 27, 2015
| isa               = x86-64
| microarch         = Skylake
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 1,800 MHz
| clock max         = 3,500 MHz
| package           = FCBGA-1356
| socket            = BGA-1356

| succession       = Yes
| predecessor      = Broadwell U
| predecessor link = intel/cores/broadwell u
| successor        = Kaby Lake U
| successor link   = intel/cores/kaby lake u
}}
'''Skylake U''' ('''SKL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Skylake|l=arch}} microarchitecture serving as a successor to {{intel|Broadwell U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Skylake U processors are fabricated on Intel's [[14 nm process]] and provide {{intel|skylake#Key_changes_from_Broadwell|a large amount of enhancements over|l=arch}} comparable Broadwell models.

== Overview ==
Skylake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Skylake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache.

{| class="wikitable"
! Standard !! Premium
|-
| 2-die configuration || 3-die configuration
|-
| GT2 Graphics || GT3 Graphics with OPC
|-
| [[File:skylake u (front; standard).png|250px]] || [[File:skylake u (front; iris).png|250px]]
|-
| [[File:skylake u (back; standard).png|250px]] || [[File:skylake u (back; iris).png|250px]]
|}
=== Common Features ===
[[File:skylake u (front; iris) angled.png|right|300px]]
All Skylake U processors have the following:

* 15 W and 28 W models
* Dual-channel Memory
** Up to LPDDR3-1866, DDR3L-1600, DDR4-2133
** Up to 32 GiB
* 12x PCIe (Except for Pentium/Celeron which only has 10)
* [[dual-core]] with 4 threads ({{intel|Celeron}} models only have 2 threads as they have {{intel|Hyper-Threading}} disabled)
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
** (Except for Pentium/Celeron which do not have AVX1/2)
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
* Graphics
** {{intel|HD Graphics 510}} (Gen 9.5 LP GT1), {{intel|HD Graphics 520}} ({{intel|Gen9.5|l=arch}} GT2), or {{intel|Iris Graphics 540}}/{{intel|Iris Graphics 550|550}} ({{intel|Gen9.5|l=arch}} GT3e)
** 3 independent displays supported
** Base frequency of 300 MHz
** Burst frequency of 1-1.1 GHz

{{clear}}

== Skylake U Processors ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc5 tc6 tc17 tc18 tc19 tc20 tc21 tc22">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="21">List of Skylake U Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="9">Main processor</th><th colspan="2">{{intel|Turbo Boost}}</th><th>Memory</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr>
{{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, 1 Core, 2 Cores, Max Mem, GPU, %Frequency, Turbo, Turbo, SMT, AVX2, TXT, TSX, vPro}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake U]]
 |?full page name
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 |?first launched
 |?release price
 |?microprocessor family
 |?core count
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 |?l3$ size
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 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?turbo frequency (2 cores)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has intel turbo boost technology 2_0
 |?has simultaneous multithreading
 |?has advanced vector extensions 2
 |?has intel trusted execution technology
 |?has transactional synchronization extensions
 |?has intel vpro technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=23:18
 |mainlabel=-
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}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake U]]}}
</table>
{{comp table end}}

== See also ==
{{intel skylake core see also}}
* {{intel|Broadwell|l=arch}}
** {{intel|Broadwell U|l=core}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Skylake U - Cores - Intel#package +
designer	Intel +
first announced	September 1, 2015 +
first launched	September 27, 2015 +
instance of	core +
isa	x86-64 +
main image	+ and +
main image caption	3-die config Iris Plus SKL-U (with OPC) + and 2-die config SKL-U +
manufacturer	Intel +
microarchitecture	Skylake +
name	Skylake U +
package	FCBGA-1356 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +