Editing intel/cores/skylake sp

{{intel title|Skylake SP|core}}
{{core
|name=Skylake SP
|image=skylake sp (basic).png
|image 2=skylake-sp (hfi).png
|caption 2=Skylake SP, with HFI
|developer=Intel
|manufacturer=Intel
|first announced=May 4, 2017
|first launched=July 11, 2017
|isa=x86-64
|microarch=Skylake (server)
|platform=Purley
|chipset=Lewisburg
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=2.0 GHz
|clock max=3.6 GHz
|package name 1=intel,fclga_3647
|predecessor=Broadwell EP
|predecessor link=intel/cores/broadwell ep
|predecessor 2=Broadwell EX
|predecessor 2 link=intel/cores/broadwell ex
|successor=Cascade Lake SP
|successor link=intel/cores/cascade lake sp
|package=FCLGA-3647
|socket=LGA-3647
|succession=Yes
}}
'''Skylake SP''' ('''{{intel|Skylake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as a successor to both {{intel|Broadwell EX|l=core}} and {{intel|Broadwell EP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], and incorporate a new {{x86|AVX-512}} [[x86]] {{x86|extension}}. Skylake SP-based chips are manufactured on an enhanced [[14 nm process|14nm+ process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. Skylake SP-based models are branded as the [[processor families]]: {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.

== Overview ==
Skylake SP processors are based on Intel's {{intel|Skylake (server)|Skylake|l=arch}} server configuration which incorporates a very large number of enhancements and improvements over its predecessor. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 TiB for extended memory models.

Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake (server)#Scalability|Skylake § Scalability|l=arch}}).

=== Common Features ===
All Skylake SP processors have the following:

* Hexa-channel memory
** 768 GiB / 1.5 TiB for extended memory variants (''M'' suffix)
** UP to DDR4-2666 MT/s
** [[ECC]] support
* '''TDP:''' 70 W to 205 W
* '''PCIe:''' x48 Lanes of PCIe Gen 3
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}
** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options

Models that are suffixed with "''T''" have extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification. Additionally, models that are suffixed with "''F''" (SKL-F) integrate the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package.


{{clear}}

== Skylake SP Processors ==
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{{comp table start}}
<table class="comptable sortable tc5 tc6 tc14">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Skylake SP Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="8">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th><th colspan="2">Scalability</th></tr>
{{comp table header 1|cols=Family, Price, Launched, Cores, Threads, Frequency, Max Turbo, %TDP, L2$, L3$, Mem Type, Max Mem, Max CPUs}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |?supported memory type
 |?max memory#GiB
 |?max cpu count
 |format=template
 |template=proc table 3
 |userparam=15
 |mainlabel=-
 |limit=75
 |sort=model number
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]]}}
</table>
{{comp table end}}

== See also ==
{{intel skylake core see also}}
* {{intel|Broadwell|l=arch}}
** {{intel|Broadwell EP|l=core}}
** {{intel|Broadwell EX|l=core}}
* AMD
** {{amd|Naples|l=core}}
chipset	Lewisburg +
designer	Intel +
first announced	May 4, 2017 +
first launched	July 11, 2017 +
instance of	core +
isa	x86-64 +
main image	+ and +
main image caption	Skylake SP, with HFI +
manufacturer	Intel +
microarchitecture	Skylake (server) +
name	Skylake SP +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket P + and LGA-3647 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +