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| {{intel title|Skylake SP|core}} | | {{intel title|Skylake SP|core}} |
| {{core | | {{core |
− | |name=Skylake SP | + | | name = Skylake SP |
− | |image=skylake sp (basic).png | + | | image = |
− | |image 2=skylake-sp (hfi).png | + | | caption = |
− | |caption 2=Skylake SP, with HFI | + | | image size = |
− | |developer=Intel | + | | image 2 = |
− | |manufacturer=Intel | + | | caption 2 = |
− | |first announced=May 4, 2017 | + | | image 2 size = |
− | |first launched=July 11, 2017 | + | | developer = Intel |
− | |isa=x86-64 | + | | manufacturer = Intel |
− | |microarch=Skylake (server) | + | | first announced = May 4, 2017 |
− | |platform=Purley
| + | | first launched = H2, 2017 |
− | |chipset=Lewisburg
| + | | isa = x86-64 |
− | |word=64 bit | + | | microarch = Skylake |
− | |proc=14 nm | + | | word = 64 bit |
− | |tech=CMOS | + | | proc = 14 nm |
− | |clock min=2.0 GHz | + | | tech = CMOS |
− | |clock max=3.6 GHz | + | | clock min = 2.0 GHz |
− | |package name 1=intel,fclga_3647 | + | | clock max = 3.6 GHz |
− | |predecessor=Broadwell EP
| + | | package = FCLGA-3647 |
− | |predecessor link=intel/cores/broadwell ep
| + | | socket = LGA-3647 |
− | |predecessor 2=Broadwell EX
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− | |predecessor 2 link=intel/cores/broadwell ex
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− | |successor=Cascade Lake SP
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− | |successor link=intel/cores/cascade lake sp
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− | |package=FCLGA-3647
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− | |socket=LGA-3647 | |
− | |succession=Yes
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− | }}
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− | '''Skylake SP''' ('''{{intel|Skylake|l=arch}} Scalable Performance''') is the code name for Intel's series of server [[multiprocessors]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as a successor to both {{intel|Broadwell EX|l=core}} and {{intel|Broadwell EP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], and incorporate a new {{x86|AVX-512}} [[x86]] {{x86|extension}}. Skylake SP-based chips are manufactured on an enhanced [[14 nm process|14nm+ process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. Skylake SP-based models are branded as the [[processor families]]: {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
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− | | |
− | == Overview ==
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− | Skylake SP processors are based on Intel's {{intel|Skylake (server)|Skylake|l=arch}} server configuration which incorporates a very large number of enhancements and improvements over its predecessor. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 TiB for extended memory models.
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− | | |
− | Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake (server)#Scalability|Skylake § Scalability|l=arch}}).
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− | | |
− | === Common Features ===
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− | All Skylake SP processors have the following:
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− | | |
− | * Hexa-channel memory
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− | ** 768 GiB / 1.5 TiB for extended memory variants (''M'' suffix)
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− | ** UP to DDR4-2666 MT/s
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− | ** [[ECC]] support
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− | * '''TDP:''' 70 W to 205 W
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− | * '''PCIe:''' x48 Lanes of PCIe Gen 3
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− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
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− | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
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− | ** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}
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− | ** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options
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− | | |
− | Models that are suffixed with "''T''" have extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification. Additionally, models that are suffixed with "''F''" (SKL-F) integrate the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package.
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− | | |
− | | |
− | {{clear}}
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− | | |
− | == Skylake SP Processors ==
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− | <!-- NOTE:
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− | This table is generated automatically from the data in the actual articles.
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− | If a microprocessor is missing from the list, an appropriate article for it needs to be
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− | created and tagged accordingly.
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| | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| + | | succession = Yes |
− | -->
| + | | predecessor = Broadwell EP |
− | {{comp table start}}
| + | | predecessor link = intel/cores/broadwell ep |
− | <table class="comptable sortable tc5 tc6 tc14">
| + | | predecessor 2 = Broadwell EX |
− | <tr class="comptable-header"><th> </th><th colspan="20">List of Skylake SP Processors</th></tr>
| + | | predecessor 2 link = intel/cores/broadwell ex |
− | <tr class="comptable-header"><th> </th><th colspan="8">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr>
| + | | successor = Kaby Lake SP |
− | {{comp table header 1|cols=Family, Price, Launched, Cores, Threads, Frequency, Max Turbo, %TDP, L2$, L3$, Mem Type, Max Mem}}
| + | | successor link = intel/cores/kaby lake sp |
− | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr>
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− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]] [[max cpu count::2]]
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− | |?full page name
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− | |?model number
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− | |?microprocessor family
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?thread count
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− | |?base frequency#GHz
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− | |?turbo frequency (1 core)#GHz
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− | |?tdp
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− | |?l2$ size
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− | |?l3$ size
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− | |?supported memory type
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− | |?max memory#GiB
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− | |format=template
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− | |template=proc table 3
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− | |userparam=14
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− | |mainlabel=-
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− | |limit=75
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− | |sort=model number
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− | }}
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− | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr>
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− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]] [[max cpu count::4]]
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− | |?full page name
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− | |?model number
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− | |?microprocessor family
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?thread count
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− | |?base frequency#GHz
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− | |?turbo frequency (1 core)#GHz
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− | |?tdp
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− | |?l2$ size
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− | |?l3$ size
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− | |?supported memory type
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− | |?max memory#GiB
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− | |format=template
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− | |template=proc table 3
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− | |userparam=14
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− | |mainlabel=-
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− | |limit=75
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− | |sort=model number
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| }} | | }} |
− | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr>
| + | '''Skylake SP''' is the code name for Intel's series of server multiprocessors based on the {{intel|Skylake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as a successor to both {{intel|Broadwell EX|l=core}} and {{intel|Broadwell EP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], and incorporate the {{x86|AVX-512}} [[x86]] {{x86|extension}}. Skylake SP-based chips are manufactured on a [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset. |
− | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]] [[max cpu count::8]] | |
− | |?full page name
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− | |?model number
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− | |?microprocessor family
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?thread count
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− | |?base frequency#GHz
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− | |?turbo frequency (1 core)#GHz
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− | |?tdp
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− | |?l2$ size
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− | |?l3$ size
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− | |?supported memory type
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− | |?max memory#GiB
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− | |format=template
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− | |template=proc table 3
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− | |userparam=14
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− | |mainlabel=-
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− | |limit=75
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− | |sort=model number
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− | }} | |
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]]}} | |
− | </table>
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− | {{comp table end}}
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− | | |
− | == See also ==
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− | {{intel skylake core see also}}
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− | * {{intel|Broadwell|l=arch}}
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− | ** {{intel|Broadwell EP|l=core}}
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− | ** {{intel|Broadwell EX|l=core}}
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− | * AMD
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− | ** {{amd|Naples|l=core}}
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