Editing intel/cores/skylake de

{{intel title|Skylake DE|core}}
{{core
|name=Skylake DE
|image=skylake-de (front).png
|developer=Intel
|manufacturer=Intel
|first announced=February 7, 2018
|first launched=February 7, 2018
|isa=x86-64
|isa family=x86
|microarch=Skylake (server)
|word=64 bit
|proc=14 nm
|clock min1,600 MHz
|clock max=2,300 MHz
|package module 1={{packages/intel/fcbga-2518}}
|predecessor=Broadwell DE
|predecessor link=intel/cores/broadwell de
}}
'''Skylake DE''' ('''SKL-DE''') is the processor core for [[Intel]]'s platform of single-chip high-performance low-power dense processors based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, succeeding {{\\|Broadwell DE}}. Skylake DE processors feature a large array of enhancements and improvements including the new {{x86|AVX-512}} extension. Skylake DE are aimed at lower power IoT, networking, and dense [[edge computing]].

== Overview ==
Skylake DE are a single-chip solution consisting of just the processor chip itself. All processors are a single-socket {{intel|BGA-2518}} package, manufacturing on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture. The chip incorporates the {{intel|Lewisburg|l=chipset}} chipset along with the microprocessor die in the same.

=== Common Features ===
For the most part, Skylake DE processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that Skylake DE chips come with {{x86|AVX-512}} along with a single execution units, similar to the low-end {{intel|Skylake SP|l=core}} models. All models have 32 [[PCIe]] lanes and have all the following features in common:

* '''Mem:''' Up 512 GiB of quad-channel DDR4 Memory
** DPC RDIMM and LRDIMM \w [[ECC]]
* '''I/O:''' 32 [[PCIe]] 3.0 Lanes
* '''TDP:''' < 110 W
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|RAS}}.

== Skylake DE Processors ==
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{{comp table start}}
<table class="comptable sortable tc4 tc5">
{{comp table header|main|10:List of Skylake DE-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|Memory}}
{{comp table header|lsep|10:Edge Server and Cloud SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Edge Server and Cloud SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |format=template
 |template=proc table 3
 |userparam=12
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|10:Network Edge and Storage SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Network Edge and Storage SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |format=template
 |template=proc table 3
 |userparam=12
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|10:Integrated QuickAssist Technology SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Integrated QuickAssist Technology SKUs]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?supported memory type
 |format=template
 |template=proc table 3
 |userparam=12
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake DE]]}}
</table>
{{comp table end}}

== Documents ==
* [[:File:d-2100-product-brief.pdf|Skylake DE Overview]]

== See also ==
{{intel skylake core see also}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Skylake DE - Cores - Intel#package +
designer	Intel +
first announced	February 7, 2018 +
first launched	February 7, 2018 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Skylake (server) +
name	Skylake DE +
package	FCBGA-2518 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
word size	64 bit (8 octets, 16 nibbles) +