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| − | {{intel title|Silverthorne|core}} | + | {{intel title|Silverthorne|l=core}} |
{{core | {{core | ||
| name = Silverthorne | | name = Silverthorne | ||
| image = silverthorne.png | | image = silverthorne.png | ||
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| image size = | | image size = | ||
| − | | image 2 = | + | | image 2 = |
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| image 2 size = | | image 2 size = | ||
| developer = Intel | | developer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| − | | first announced = April | + | | first announced = April 2, 2008 |
| first launched = April 2, 2008 | | first launched = April 2, 2008 | ||
| isa = x86-32 | | isa = x86-32 | ||
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| socket 2 = BGA-441 | | socket 2 = BGA-441 | ||
| − | | succession = | + | | succession = <!-- yes for succession info --> |
| − | | predecessor = | + | | predecessor = |
| − | | predecessor link = | + | | predecessor link = |
| − | | successor = | + | | successor = |
| − | | successor link = | + | | successor link = |
}} | }} | ||
| − | '''Silverthorne''' is the core name for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture | + | '''Silverthorne''' is the core name for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture. Those ultra-low power chips were manufactured on Intel's [[45 nm process]] and were specifically aimed for the [[Mobile Internet device]] (MID) market. Silverthorne-based processors are {{arch|32}} [[x86]] single core processors with TDP ranging from just 650 mW to 2.5 W. |
== Overview == | == Overview == | ||
| − | All models are based on {{intel|Bonnell|l=arch}} manufactured on a [[45 nm process]] and implement [[x86-32]] with no {{arch|64}} support. | + | All models are based on {{intel|Bonnell|l=arch}} manufactured on a [[45 nm process]] and implement [[x86-32]] with no {{arch|64}} support. |
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* '''TDP:''' 650 mW - 2.5 W | * '''TDP:''' 650 mW - 2.5 W | ||
* '''ISA:''' Everything up to {{x86|SSSE3}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}) | * '''ISA:''' Everything up to {{x86|SSSE3}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}) | ||
* '''Tech:''' All models have {{intel|EIST}} | * '''Tech:''' All models have {{intel|EIST}} | ||
| − | * '''Bus:''' 400-533 | + | * '''Bus:''' 400-533 MHz [[FSB]] |
* {{intel|Poulsbo|l=chipset}} Chipset | * {{intel|Poulsbo|l=chipset}} Chipset | ||
* 47,212,207 transistors | * 47,212,207 transistors | ||
| − | * 3.1 mm x 7.8 mm | + | * 24.2 mm² die size (3.1 mm x 7.8 mm) |
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== Members == | == Members == | ||
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== See Also == | == See Also == | ||
| − | {{intel | + | * {{intel|Bonnell|l=arch}} |
* {{amd|Geode NX}} | * {{amd|Geode NX}} | ||
Facts about "Silverthorne - Cores - Intel"
| designer | Intel + |
| first announced | April 18, 2007 + |
| first launched | April 2, 2008 + |
| instance of | core + |
| isa | x86-32 + |
| main image |  + and .png) + |
| main image caption | Packaged in FCBGA-441 (13x14) + and Packaged in FCBGA-437 (22x22) + |
| manufacturer | Intel + |
| microarchitecture | Bonnell + |
| name | Silverthorne + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |
.png){kind=link}