From WikiChip
Editing intel/cores/kaby lake s

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Kaby Lake S|core}}
 
{{intel title|Kaby Lake S|core}}
 
{{core
 
{{core
|name=Kaby Lake S
+
| name             = Kaby Lake S
|image=kaby lake s (front).png
+
| developer         = Intel
|image 2=kaby lake s (back).png
+
| manufacturer     = Intel
|developer=Intel
+
| first announced   = January 3, 2017
|manufacturer=Intel
+
| first launched   = January 3, 2017
|first announced=January 3, 2017
+
| isa               = x86-64
|first launched=January 3, 2017
+
| microarch         = Kaby Lake
|isa=x86-64
+
| word             = 64 bit
|isa family=x86
+
| proc             = 14 nm
|microarch=Kaby Lake
+
| tech             = CMOS
|word=64 bit
+
| clock min         =  
|proc=14 nm
+
| clock max         =
|tech=CMOS
+
| package          = FCLGA-1151
|clock min=2,400 MHz
+
| socket            = LGA-1151
|clock max=4,200 MHz
+
 
|predecessor=Skylake S
+
| succession      = Yes
|predecessor link=intel/cores/skylake s
+
| predecessor     = Skylake S
|successor=Coffee Lake S
+
| predecessor link = intel/cores/skylake s
|successor link=intel/cores/coffee lake s
+
| successor       = Cannonlake S
|package=FCLGA-1151
+
| successor link   = intel/cores/cannonlake s
|socket=LGA-1151
 
|succession=Yes
 
 
}}
 
}}
 
'''Kaby Lake S''' ('''KBL-S''') is the name of the core for [[Intel]]'s mainstream performance line of processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake S|l=core}} core. These chips are primarily targeted towards desktop performance to value computers, AiOs, and minis. Kaby Lake S processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm+ process]] and provide {{intel|kaby_lake#Key_changes_from_Skylake|slight enhancements over|l=arch}} comparable Skylake models.
 
'''Kaby Lake S''' ('''KBL-S''') is the name of the core for [[Intel]]'s mainstream performance line of processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake S|l=core}} core. These chips are primarily targeted towards desktop performance to value computers, AiOs, and minis. Kaby Lake S processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm+ process]] and provide {{intel|kaby_lake#Key_changes_from_Skylake|slight enhancements over|l=arch}} comparable Skylake models.
 
== Overview ==
 
Kaby Lake S based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Kaby Lake S are {{intel|LGA-1151|Socket LGA-1151}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake S|l=core}}) {{intel|Sunrise Point}} via a firmware upgrade. The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane.
 
 
=== Common Features ===
 
All Kaby Lake S processors have the following:
 
 
* Dual-channel Memory
 
** Up to DDR3L-1600, DDR4-2400
 
** Up to 64 GiB
 
* 16x PCIe (4 of the 20 are used by the bus as described above)
 
* [[dual-core|2]] to [[quad-core|4]] core with 2 to 8 threads (not all S models support {{intel|Hyper-Threading}})
 
* Everything up to SSE4.2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES) (not all S models support {{x86|AVX2}})
 
* Graphics
 
** {{intel|HD Graphics 610}} ({{intel|Gen9.5|l=arch}} GT1) or {{intel|HD Graphics 630}} ({{intel|Gen9.5|l=arch}} GT2)
 
** Base frequency of 350 MHz
 
** Burst frequency of 1-1.15 GHz
 
{{clear}}
 
 
== Kaby Lake S Processors ==
 
<!-- NOTE:
 
          This table is generated automatically from the data in the actual articles.
 
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
          created and tagged accordingly.
 
 
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
{{comp table start}}
 
<table class="comptable sortable tc15 tc16 tc17 tc18 tc19">
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Kaby Lake S Processors</th></tr>
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
 
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th data-sort-type="number">C</th><th data-sort-type="number">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake S]]
 
|?full page name
 
|?model number
 
|?first launched
 
|?release price
 
|?microprocessor family
 
|?core count
 
|?thread count
 
|?l3$ size
 
|?tdp
 
|?base frequency#GHz
 
|?turbo frequency (1 core)#GHz
 
|?max memory#GiB
 
|?integrated gpu
 
|?integrated gpu base frequency
 
|?integrated gpu max frequency
 
|?has intel turbo boost technology 2_0
 
|?has simultaneous multithreading
 
|?has advanced vector extensions 2
 
|?has intel trusted execution technology
 
|?has transactional synchronization extensions
 
|?has intel vpro technology
 
|?has_intel_vt-d_technology
 
|format=template
 
|template=proc table 3
 
|searchlabel=
 
|sort=microprocessor family, model number
 
|order=asc,asc
 
|userparam=22:16
 
|mainlabel=-
 
|valuesep=,
 
|limit=100
 
}}
 
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake S]]}}
 
</table>
 
{{comp table end}}
 
 
== See also ==
 
[[File:kaby lake s (angle).png|right|thumb]]
 
{{intel kaby lake core see also}}
 
* {{intel|Skylake|l=arch}}
 
** {{intel|Skylake S|l=core}}
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
designerIntel +
first announcedJanuary 3, 2017 +
first launchedJanuary 3, 2017 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:kaby lake s (front).png + and File:kaby lake s (back).png +
manufacturerIntel +
microarchitectureKaby Lake +
nameKaby Lake S +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +