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|name=Kaby Lake R
 
|name=Kaby Lake R
 
|no image=Yes
 
|no image=Yes
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|image=kaby lake r (front).png
 
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|image size=250px
 
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|caption=Package front side
 
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|image 2=kaby lake r (back).png
 
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|image 2 size=250px
 
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|caption 2=Package back side
 
 
|developer=Intel
 
|developer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|proc=14 nm
 
|proc=14 nm
 
|tech=CMOS
 
|tech=CMOS
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|clock min=1,600 MHz
 
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|clock max=1,900 MHz
 
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|package module 1={{packages/intel/fcbga-1356}}
 
 
|predecessor=Kaby Lake U
 
|predecessor=Kaby Lake U
 
|predecessor link=intel/cores/kaby lake u
 
|predecessor link=intel/cores/kaby lake u
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|successor=Whiskey Lake U
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|successor=Coffee Lake U
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|successor link=intel/cores/whiskey lake u
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|successor link=intel/cores/coffee lake u
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|successor 2=Cannon Lake U
 
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|successor 2 link=intel/cores/cannon lake u
 
 
}}
 
}}
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'''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]] and feature double the core count of the previous generation.
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'''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Coffee Lake U processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]].
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Although those microprocessors are still based on {{intel|Kaby Lake|l=arch}}, Intel has branded them as 8th Generation Core. Those processors are also the first to feature quad-cores within the 15 Watt TDP class of mobile processors.
 
  
 
== Overview ==
 
== Overview ==
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* Dual-channel Memory
 
* Dual-channel Memory
 
** Up to DDR4-2400, LPDDR3-2133
 
** Up to DDR4-2400, LPDDR3-2133
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** 32 GiB
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** Up to 32 GiB
 
* 12x PCIe
 
* 12x PCIe
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* [[Quad-core]] with 8 threads
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* [[quad-core]] with 8 threads
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
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* {{intel|Turbo Boost}}, {{intel|Hyper-Threading}}, {{intel|Software Guard}}, {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|OS Guard}}, {{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
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* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
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* Support [[AHCI]], [[High Definition Audio]], 6x [[USB 3.0]] ports, 10x [[USB 2.0]] ports, 4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
 
 
* Graphics
 
* Graphics
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** {{intel|UHD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2)
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** {{intel|HD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2)({{intel|Gen9.5|l=arch}} GT3e)
 
** 3 independent displays supported
 
** 3 independent displays supported
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** Base frequency of 300 MHz
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** Base frequency of 350 MHz
 
** Burst frequency of 1-1.15 GHz
 
** Burst frequency of 1-1.15 GHz
  
 
{{clear}}
 
{{clear}}
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== Compiler support ==
 
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{| class="wikitable"
 
−
|-
 
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! Compiler !! Arch-Specific || Arch-Favorable
 
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|-
 
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| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 
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|-
 
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| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 
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|-
 
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| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 
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|-
 
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| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
 
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|}
 
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=== CPUID ===
 
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{| class="wikitable tc1 tc2 tc3 tc4 tc5"
 
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
 
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|-
 
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| rowspan="2" | {{intel|Kaby Lake R|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xA
 
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|-
 
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| colspan="5" | Family 6 Model 142 Stepping 10
 
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|}
 
−
 
  
 
== Kaby Lake R Processors ==
 
== Kaby Lake R Processors ==
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-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
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<table class="comptable sortable tc5 tc6">
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<table class="comptable sortable tc16 tc17 tc18 tc19 tc20 tc21">
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="21">List of Kaby Lake R Processors</th></tr>
 
<tr class="comptable-header"><th>&nbsp;</th><th colspan="21">List of Kaby Lake R Processors</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="11">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr>
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{{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %TDP, Frequency, %{{intel|turbo boost|Turbo}}, Max Mem, Name, Frequency, Turbo}}
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{{comp table header 1|cols=Launched, Price, Family, Cores, Threads, L3$, TDP, Frequency, {{intel|turbo boost|Turbo}}, Max Mem, Name, Frequency, Turbo}}
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake R]]
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake R]]
 
  |?full page name
 
  |?full page name
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  |sort=microprocessor family, model number
 
  |sort=microprocessor family, model number
 
  |order=asc,asc
 
  |order=asc,asc
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  |userparam=15
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  |userparam=14
 
  |mainlabel=-
 
  |mainlabel=-
 
  |limit=100
 
  |limit=100
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</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
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== Documents ==
 
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* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]]
 
  
 
== See also ==
 
== See also ==
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[[File:kaby lake r (front, angled).png|right|175px]]
 
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[[File:kaby lake r (back, angled).png|right|175px]]
 
 
{{intel kaby lake core see also}}
 
{{intel kaby lake core see also}}

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Facts about "Kaby Lake R - Cores - Intel"
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Kaby Lake R - Cores - Intel#package +
designerIntel +
first announcedAugust 21, 2017 +
first launchedAugust 21, 2017 +
instance ofcore +
isax86-64 +
main imageFile:kaby lake r (back).png + and File:kaby lake r (front).png +
main image captionPackage front side + and Package back side +
manufacturerIntel +
microarchitectureKaby Lake +
nameKaby Lake R +
packageFCBGA-1356 +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +