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{{core
 
{{core
 
|name=Ice Lake Y
 
|name=Ice Lake Y
|image=File:ice lake y (front).png
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|no image=Yes
|caption=Ice Lake Y, front package
 
|back image=File:ice lake y (back).png
 
 
|developer=Intel
 
|developer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|first announced=December, 2018
 
|first launched=May 27, 2019
 
 
|isa=x86-64
 
|isa=x86-64
 
|microarch=Ice Lake
 
|microarch=Ice Lake
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|proc=10 nm
 
|proc=10 nm
 
|tech=CMOS
 
|tech=CMOS
|package name 1=intel,fcbga_1377
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|package name 1=intel,bga_1377
 
|predecessor=Amber Lake Y
 
|predecessor=Amber Lake Y
 
|predecessor link=intel/cores/amber lake y
 
|predecessor link=intel/cores/amber lake y
|successor=Tiger Lake Y
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|successor=Ice Lake Y
|successor link=intel/cores/tiger lake y
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|successor link=intel/cores/ice lake y
 
}}
 
}}
'''Ice Lake Y''' ('''ICL-Y''') is codename for [[Intel]]'s extremely-low power line of processors based on the {{intel|Ice Lake|l=arch}} microarchitecture serving as a successor to the {{\\|Amber Lake Y}} core. These chips are primarily targeted towards 2-in-1s detachable, tablets, and computer sticks. Ice Lake Y processors are fabricated on Intel's enhanced [[10 nm process|10nm+ process]] and provide {{intel|ice_lake_(client)#Key_changes_from_Cannon_Lake.2FSkylake|significant amount of enhancements}} over the prior generation.
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'''Ice Lake Y''' ('''ICL-Y''') is the name of the core for [[Intel]]'s extremly-low power line of processors based on the {{intel|Ice Lake|l=arch}} microarchitecture serving as a successor to the {{intel|Cannon Lake Y|l=core}} core. These chips are primarily targeted towards 2-in-1s detachable, tablets, and computer sticks. Cannon Lake Y processors are fabricated on Intel's enhanced [[10 nm process|10nm+ process]] and come at slightly higher clock frequencies.
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{{future information}}
  
  
 
== Overview ==
 
== Overview ==
Ice Lake Y based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Ice Lake Y processors use {{intel|FCBGA-1377}} packages.
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{{empty section}}
  
 
=== Common Features ===
 
=== Common Features ===
All Ice Lake Y processors have the following:
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{{empty section}}
 
 
* Quad/dual-channel Memory
 
** Up to dual-channel (2x64b) DDR4-3200
 
** Up to quad-channel (4x32b) LPDDR4X-3733
 
** 32 GiB
 
* 4x Thunderbolt 3 (USB 3.2 Gen 2x1 (10 Gb/s), Thunderbolt 3, DisplayPort 1.4)
 
* [[Quad-core]] with 8 threads (2 cores for lowest-end model)
 
* Everything up to AVX512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2, AVX512)
 
* {{intel|Turbo Boost}}, {{intel|Hyper-Threading}}, {{intel|Software Guard}}, {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|OS Guard}}, {{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
 
* Support [[AHCI]], [[High Definition Audio]], 6x [[USB 2.0]] ports, 2x [[SATA III]]
 
* Graphics
 
** {{intel|Iris Plus Graphics}},{{intel|UHD Graphics}} ({{intel|Gen11|l=arch}} GT2)
 
** 3 independent displays supported
 
** Base frequency of 300 MHz
 
** Burst frequency of 0.9-1.15 GHz
 
 
 
 
{{clear}}
 
{{clear}}
  
 
== Ice Lake Y Processors ==
 
== Ice Lake Y Processors ==
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{{future information}}
 +
 
<!-- NOTE:  
 
<!-- NOTE:  
 
           This table is generated automatically from the data in the actual articles.
 
           This table is generated automatically from the data in the actual articles.
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-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
<table class="comptable sortable tc4 tc5">
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<table class="comptable sortable tc5 tc6">
{{comp table header|main|11:List of Ice Lake Y Processors}}
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{{comp table header|main|12:List of Ice Lake Y Processors}}
{{comp table header|main|8:Main processor|3:Integrated Graphics}}
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{{comp table header|main|9:Main processor|3:Integrated Graphics}}
{{comp table header|cols|Launched|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|Name|%Frequency|%Turbo}}
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{{comp table header|cols|Price|Launched|Family|Cores|Threads|L3$|%TDP|%Frequency|%Turbo|Name|%Frequency|%Turbo}}
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Ice Lake Y]]
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Ice Lake Y]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
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|?release price
 
  |?first launched
 
  |?first launched
 
  |?microprocessor family
 
  |?microprocessor family
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  |?l3$ size
 
  |?l3$ size
 
  |?tdp
 
  |?tdp
  |?base frequency#MHz
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  |?base frequency#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?integrated gpu
 
  |?integrated gpu
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  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
  |userparam=13
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  |userparam=14
 
  |mainlabel=-
 
  |mainlabel=-
 
}}
 
}}
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</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
 
=== SKU Comparison ===
 
Below are a number of SKU comparison graphs based on their specifications.
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake Y]]
 
|?core count
 
|?base frequency
 
|charttitle=Cores vs. Base Frequency
 
|numbersaxislabel=Frequency (MHz)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake Y]]
 
|?core count
 
|?turbo frequency (1 core)
 
|charttitle=Cores vs. Turbo Frequency
 
|numbersaxislabel=Frequency (MHz)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake Y]]
 
|?core count
 
|?tdp
 
|charttitle=Cores vs. TDP
 
|numbersaxislabel=TDP (W)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake Y]]
 
|?turbo frequency (1 core)
 
|?tdp
 
|charttitle=Frequency vs. TDP
 
|numbersaxislabel=TDP (W)
 
|labelaxislabel=Frequency (MHz)
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
{{clear}}
 
  
 
== See also ==
 
== See also ==
 
{{intel ice lake core see also}}
 
{{intel ice lake core see also}}

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back imageFile:ice lake y (back).png +
designerIntel +
first announcedDecember 2018 +
first launchedMay 27, 2019 +
instance ofcore +
isax86-64 +
main imageFile:ice lake y (front).png +
main image captionIce Lake Y, front package +
manufacturerIntel +
microarchitectureIce Lake +
nameIce Lake Y +
packageFCBGA-1377 +
process10 nm (0.01 μm, 1.0e-5 mm) +
socketType 3 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +