From WikiChip
Editing intel/cores/ice lake u
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 9: | Line 9: | ||
|first announced=December, 2018 | |first announced=December, 2018 | ||
|first launched=May 27, 2019 | |first launched=May 27, 2019 | ||
+ | |fate=Delayed | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 26: | Line 27: | ||
|contemporary link=intel/cores/comet lake u | |contemporary link=intel/cores/comet lake u | ||
}} | }} | ||
− | '''Ice Lake U''' ('''ICL-U''') is the code name for [[Intel]]'s line of low-power mobile processors based on the {{intel|Ice Lake|l=arch}} microarchitecture, succeeding {{\\|Cannon Lake U}} | + | '''Ice Lake U''' ('''ICL-U''') is the code name for [[Intel]]'s line of low-power mobile processors based on the {{intel|Ice Lake|l=arch}} microarchitecture, succeeding both {{\\|Cannon Lake U}} and {{\\|Whiskey Lake U}}. These chips are primarily targeted towards mainstream through premium tablets, thin-and-light, and other performance mobile devices. Ice Lake U processors are fabricated on Intel's enhanced [[10 nm process|10nm+ process]] and provide {{intel|ice_lake_(client)#Key_changes_from_Cannon_Lake.2FSkylake|significant amount of enhancements}} over the prior generation. |
− | |||
== Overview == | == Overview == | ||
− | + | {{empty section}} | |
=== Common Features === | === Common Features === | ||
− | + | {{empty section}} | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
{{clear}} | {{clear}} | ||
Line 89: | Line 73: | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== See also == | == See also == | ||
{{intel ice lake core see also}} | {{intel ice lake core see also}} |
Facts about "Ice Lake U - Cores - Intel"
back image | + |
designer | Intel + |
first announced | December 2018 + |
first launched | May 27, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + |
main image caption | Ice Lake U, front package + |
manufacturer | Intel + |
microarchitecture | Ice Lake + |
name | Ice Lake U + |
package | FCBGA-1526 + |
platform | Ice Lake + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
socket | Type 4 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |