Editing intel/cores/coffee lake u

{{intel title|Coffee Lake U|core}}
{{core
|name=Coffee Lake U
|no image=Yes
|developer=Intel
|manufacturer=Intel
|first announced=April 2, 2018
|first launched=April 2, 2018
|isa=x86-64
|isa family=x86
|microarch=Coffee Lake
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=2,300 MHz
|clock max=3,000 MHz
|package module 1={{packages/intel/fcbga-1528}}
|predecessor=Kaby Lake U
|predecessor link=intel/cores/kaby lake U
|successor=Ice Lake U
|successor link=intel/cores/ice lake u
|contemporary=Whiskey Lake U
|contemporary link=intel/cores/whiskey lake u
}}
'''Coffee Lake U''' ('''CFL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Coffee Lake|l=arch}} microarchitecture serving as a successor to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Coffee Lake U processors are fabricated on Intel's 3rd generation enhanced [[14 nm lithography process|14nm++ process]].

== Overview ==
Coffee Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP) along with the [[eDRAM]]. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Coffee LAke U processors use {{intel|BGA-1356|Socket BGA-1528}} and incorporate 128 MiB of side cache.

=== Common Features ===
[[File:kaby lake u (front; iris) angled.png|right|300px]]
All Coffee Lake U processors have the following:

* Dual-channel Memory
** Up to DDR4-2400, LPDDR3-2133
** Up to 64 GiB
* 16x PCIe
* [[dual-core]]/[[quad-core]] with 2 threads per core
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
** (Except for Pentium/Celeron which do not have AVX1/2)
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
* Graphics
** {{intel|Iris Plus Graphics 655}} ({{intel|Gen9.5|l=arch}} GT3e)
** 128 MiB of eDRAM side cache
** 3 independent displays supported
** Base frequency of 300 MHz
** Burst frequency of 1.05-1.2 GHz

{{clear}}

== Coffee Lake U Processors ==
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{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|18:List of Coffee Lake U Processors}}
{{comp table header|main|11:Main processor|3:Integrated Graphics}}
{{comp table header|cols|Launched|Price|Family|Cores|Threads|%L3$|%L4$|%TDP|%Frequency|%Turbo|%TV Boost|Name|%Frequency|%Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake U]]
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 |?first launched
 |?release price
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
 |?l4$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
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 |?integrated gpu max frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=16
 |mainlabel=-
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}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Coffee Lake U]]}}
</table>
{{comp table end}}

== See also ==
{{intel coffee lake core see also}}
* {{intel|Kaby Lake|l=arch}}
** {{intel|Kaby Lake R|l=core}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Coffee Lake U - Cores - Intel#package +
designer	Intel +
first announced	April 2, 2018 +
first launched	April 2, 2018 +
instance of	core +
isa	x86-64 +
isa family	x86 +
manufacturer	Intel +
microarchitecture	Coffee Lake +
name	Coffee Lake U +
package	FCBGA-1528 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +