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Latest revision | Your text | ||
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* Dual-channel Memory | * Dual-channel Memory | ||
− | ** DDR4- | + | ** DDR4-2666 ({{intel|Core i3}} are limited to DDR4-2400) |
** 64 GiB | ** 64 GiB | ||
* 16x PCIe (4 of the 20 are used by the bus as described above) | * 16x PCIe (4 of the 20 are used by the bus as described above) | ||
Line 39: | Line 39: | ||
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | * Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | ||
* Graphics | * Graphics | ||
− | ** UHD Graphics ({{intel|Gen9.5|l=arch}} | + | ** {{intel|UHD Graphics 630}} ({{intel|Gen9.5|l=arch}} GT2) |
** Base frequency of 350 MHz | ** Base frequency of 350 MHz | ||
** Burst frequency of 1-1.15 GHz | ** Burst frequency of 1-1.15 GHz |
Facts about "Coffee Lake S - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Coffee Lake S - Cores - Intel#package + |
designer | Intel + |
first announced | September 24, 2017 + |
first launched | October 5, 2017 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + and + |
main image caption | Package front side + and Package back side + |
manufacturer | Intel + |
microarchitecture | Coffee Lake + |
name | Coffee Lake S + |
package | FCLGA-1151 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-1151 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |