Editing intel/cores/cascade lake w

{{intel title|Cascade Lake W|core}}
{{core
|name=Cascade Lake W
|image=intel skylake w (front).png
|developer=Intel
|manufacturer=Intel
|first announced=2019
|first launched=2019
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Glacier Falls
|word=64 bit
|proc=14 nm
|package name 1=intel,fclga_2066
|predecessor=Skylake W
|predecessor link=intel/cores/skylake_w
}}
'''Cascade Lake W''' ('''Cascade Lake Workstations'''; '''CLS-W''') is codename for [[Intel]]'s enterprise workstation microprocessor line based on the {{intel|Cascade Lake|l=arch}} microarchitecture, succeeding {{\\|Skylake W}}. Cascade Lake W processors feature a {{intel|Cascade Lake#Key changes from Skylake|number of enhancements|l=arch}} including a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support.

== Overview ==
Cascade LAke W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the C422 chipset. All processors are socket {{intel|Socket R4}} (LGA-2066), manufactured on Intel's [[14 nm process|enhanced 14++ nm process]] based on the {{intel|Cascade Lake|Skylake|l=arch}} microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as {{intel|vPro}}, {{intel|Volume Management Device}} (VMD), and RAS.

=== Common Features ===
For the most part, Cascade Lake W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that the Skylake W come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models (with the exception of the two low-end models). All models have 48 [[PCIe]] lanes and have all the following features in common:

* '''Mem:''' 512 GiB of quad-channel DDR4-2933 ECC Memory
** DPC RDIMM and LRDIMM \w [[ECC]]
* '''I/O:''' 48 [[PCIe]] 3.0 Lanes
* '''TDP:''' 160 W - 205 W
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).


== Cascade Lake W Processors ==
Note that for the lower [[core-count]]  models, the [[L3 cache]] size is larger than it would otherwise be due to additional cache slices being enabled from disabled [[physical core|cores]].

{{future information}}

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{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|10:List of Cascade Lake W-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|AVX-512 Units}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake W]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?number of avx-512 execution units
 |format=template
 |template=proc table 3
 |userparam=12
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake W]]}}
</table>
{{comp table end}}

== See also ==
{{intel cascade lake core see also}}
designer	Intel +
first announced	October 7, 2019 +
first launched	October 7, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Cascade Lake +
name	Cascade Lake W +
package	FCLGA-2066 +
platform	Glacier Falls +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket R4 +
word size	64 bit (8 octets, 16 nibbles) +