Editing intel/cores/cascade lake sp

{{intel title|Cascade Lake SP|core}}
{{core
|name=Cascade Lake SP
|image=cascade lake sp (front).png
|developer=Intel
|manufacturer=Intel
|first announced=April 2, 2019
|first launched=April 2, 2019
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|word=64 bit
|proc=14 nm
|tech=CMOS
|package name 1=intel,fclga_3647
|predecessor=Skylake SP
|predecessor link=intel/cores/skylake sp
|successor=Ice Lake SP
|successor link=intel/cores/ice lake sp
|contemporary=Cascade Lake R
|contemporary link=intel/cores/cascade lake r
}}
'''Cascade Lake SP''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as the successor to {{intel|Skylake SP|l=core}}. These chips support up to 8-way multiprocessing, up to [[28 cores]], incorporate a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake SP-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset.

Cascade Lake SP-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}} [[processor families]].


== Overview ==
Cascade Lake SP processors are based on Intel's {{intel|Cascade Lake|l=arch}} microarchitecture which brings a modest frequency improvement due to an enhancement process technology along with {{intel|DL Boost}}, an {{x86|extension}} designed to speed up machine learning algorithms. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel ? GiB of DDR4 ECC memory or ? TiB for extended memory models. Cascade Lake also brings support for [[persistent memory]].

As with {{\\|Skylake SP}}, Cascade Lake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|cascade lake#Scalability|Cascade Lake § Scalability|l=arch}}).

=== Common Features ===
All Cascade Lake SP processors have the following:

* Hexa-channel memory
** 1 TiB, 2 TiB medium memory support variants (''M'' suffix), and 4.5 TiB for extended memory variants (''L'' suffix)
** UP to DDR4-2933 MT/s
** [[ECC]] support
* '''TDP:''' 85 W to 205 W
* '''PCIe:''' x48 Lanes of PCIe Gen 3
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}
** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options

Models that are suffixed with "''T''" have extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification. Additionally, models that are suffixed with "''F''" (CSL-F) integrate the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package.


{{clear}}

== Cascade Lake SP Processors ==
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           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc5 tc6 tc14">
{{comp table header|main|12:List of Cascade Lake SP-based Processors}}
{{comp table header|main|8:Main Processor|1:Cache|2:Memory}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Max Turbo|%TDP|L3$|Mem Type|Max Mem}}
{{comp table header|lsep|25:[[Uniprocessors]] (1-way)}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::1]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l3$ size
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
 |limit=75
 |valuesep=,
 |sort=model number
}}
{{comp table header|lsep|25:[[Multiprocessors]] (2-way)}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::2]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l3$ size
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
 |limit=75
 |valuesep=,
 |sort=model number
}}
{{comp table header|lsep|25:[[Multiprocessors]] (4-way)}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::4]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l3$ size
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
 |limit=75
 |valuesep=,
 |sort=model number
}}
{{comp table header|lsep|25:[[Multiprocessors]] (8-way)}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::8]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l3$ size
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
 |limit=75
 |valuesep=,
 |sort=model number
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]]}}
</table>
{{comp table end}}

== See also ==
{{intel cascade lake core see also}}
@@ Line 29: / Line 29: @@
 == Overview ==
-Cascade Lake SP processors are based on Intel's {{intel|Cascade Lake|l=arch}} microarchitecture which brings a modest frequency improvement due to an enhancement process technology along with {{intel|DL Boost}}, an {{x86|extension}} designed to speed up machine learning algorithms. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-channel 1 TiB of DDR4 ECC memory with up to 2 TiB and even 4.5 TiB for the medium memory and large memory tiers extended memory models. Cascade Lake also brings support for [[persistent memory]].
+Cascade Lake SP processors are based on Intel's {{intel|Cascade Lake|l=arch}} microarchitecture which brings a modest frequency improvement due to an enhancement process technology along with {{intel|DL Boost}}, an {{x86|extension}} designed to speed up machine learning algorithms. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel ? GiB of DDR4 ECC memory or ? TiB for extended memory models. Cascade Lake also brings support for [[persistent memory]].
 As with {{\\|Skylake SP}}, Cascade Lake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|cascade lake#Scalability|Cascade Lake § Scalability|l=arch}}).
@@ Line 47: / Line 47: @@
 ** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options
-{{clear}}
+Models that are suffixed with "''T''" have extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification. Additionally, models that are suffixed with "''F''" (CSL-F) integrate the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package.
-=== Naming Scheme ===
-Cascade Lake SKUs follow the following naming scheme.
-:[[File:cascade lake naming scheme.svg|600px]]
+{{clear}}
-Where,
-* "''F''" suffix integrates the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package
-* "''L''" suffix indicates the SKU is a large memory (4.5 TiB) tier SKU
-* "''M''" suffix indicates the SKU is a medium memory (2 TiB) tier SKU
-* "''N''" suffix indicates the SKU is a networking-specialized model
-* "''S''" suffix indicates the SKU is a search application-specialized model
-* "''T''" suffix indicates that SKU has an extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification
-* "''U''" suffix indicates the SKU is a single-socket model (even if part of the [[Xeon Gold]] family that normally supports up two 4-way [[SMP]])
-* "''V''" suffix indicates the SKU targets the VM density value market
-* "''Y''" suffix indicates the SKU has {{intel|Speed Select Technology}} (SST)
 == Cascade Lake SP Processors ==
@@ Line 174: / Line 160: @@
 </table>
 {{comp table end}}
-=== SKU Comparison ===
-Below are a number of SKU comparison graphs based on their specifications.
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]]
- |?core count
- |?base frequency
- |charttitle=Cores vs. Base Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]]
- |?core count
- |?turbo frequency (1 core)
- |charttitle=Cores vs. Turbo Frequency
- |numbersaxislabel=Frequency (MHz)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]]
- |?core count
- |?tdp
- |charttitle=Cores vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Core Count
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-<div style="float: left; margin: 10px">
-{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]]
- |?turbo frequency (1 core)
- |?tdp
- |charttitle=Frequency vs. TDP
- |numbersaxislabel=TDP (W)
- |labelaxislabel=Frequency (MHz)
- |height=400
- |width=400
- |theme=vector
- |group=property
- |grouplabel=subject
- |charttype=scatter
- |format=jqplotseries
- |mainlabel=-
-}}
-</div>
-{{clear}}
 == See also ==
 {{intel cascade lake core see also}}
chipset	Lewisburg +
designer	Intel +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Cascade Lake +
name	Cascade Lake SP +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket P + and LGA-3647 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +