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'''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform.
 
'''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform.
  
Cascade Lake AP-based processors are branded as {{intel|Xeon Platinum}} 9200-series.
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 +
{{future information}}
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== Overview ==
 
== Overview ==
Cascade Lake AP comprise of two {{intel|Cascade Lake|l=arch}} dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels.
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Cascade Lake AP comprise of multiple {{intel|Cascade Lake|l=arch}} dies in a single BGA-5903 package. Those processors support up to 48 cores, 96 threads, and up to 12 DDR4 channels.
 
 
Cascade Lake AP processors cannot be purchased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).
 
  
 
=== Common Features ===
 
=== Common Features ===
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** ECC support
 
** ECC support
 
* '''TDP:''' 250 W to 400 W
 
* '''TDP:''' 250 W to 400 W
* '''PCIe:''' x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
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* '''PCIe:''' x80 Lanes of PCIe Gen 3
 
* '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}})
 
* '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}})
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}
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-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
<table class="comptable sortable tc3 tc4 tc5 tc6 tc7 tc8">
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<table class="comptable sortable tc4 tc5 tc11">
 
{{comp table header|main|11:List of Cascade Lake AP-based Processors}}
 
{{comp table header|main|11:List of Cascade Lake AP-based Processors}}
{{comp table header|cols|Launched|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}}
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{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}}
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 
  |?first launched
 
  |?first launched
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|?release price
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
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  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
  |userparam=10
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  |userparam=11
 
  |sort=model number
 
  |sort=model number
 
  |mainlabel=-
 
  |mainlabel=-
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{{comp table end}}
 
{{comp table end}}
  
=== SKU Comparison ===
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== Cascade Lake AP Processors ==
Below are a number of SKU comparison graphs based on their specifications.
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{{empty section}}
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
|?core count
 
|?base frequency
 
|charttitle=Cores vs. Base Frequency
 
|numbersaxislabel=Frequency (MHz)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
|?core count
 
|?turbo frequency (1 core)
 
|charttitle=Cores vs. Turbo Frequency
 
|numbersaxislabel=Frequency (MHz)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
|?core count
 
|?tdp
 
|charttitle=Cores vs. TDP
 
|numbersaxislabel=TDP (W)
 
|labelaxislabel=Core Count
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
 
<div style="float: left; margin: 10px">
 
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 
|?turbo frequency (1 core)
 
|?tdp
 
|charttitle=Frequency vs. TDP
 
|numbersaxislabel=TDP (W)
 
|labelaxislabel=Frequency (MHz)
 
|height=400
 
|width=400
 
|theme=vector
 
|group=property
 
|grouplabel=subject
 
|charttype=scatter
 
|format=jqplotseries
 
|mainlabel=-
 
}}
 
</div>
 
 
 
{{clear}}
 
 
 
== Documents ==
 
* [[:File:S9200WK-Reference-Design-Guide.pdf|S9200WK reference design guide]]
 
  
 
== See also ==
 
== See also ==
 
{{intel cascade lake core see also}}
 
{{intel cascade lake core see also}}

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designerIntel +
instance ofcore +
isax86-64 +
main imageFile:cascade lake ap (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake AP +
packageFCBGA-5903 +
platformWalker Pass +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +