Editing intel/cores/amber lake y

{{intel title|Amber Lake Y|core}}
{{core
|name=Amber Lake Y
|no image=Yes
|image=kaby lake y (front).png
|image 2=kaby lake y (back).png
|developer=Intel
|manufacturer=Intel
|first announced=June 4, 2018
|first launched=August 28, 2018
|isa=x86-64
|isa family=x86
|microarch=Amber Lake
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=1,100 MHz
|clock max=1,500 MHz
|predecessor=Kaby Lake Y
|predecessor link=intel/cores/kaby lake y
|successor=Ice Lake Y
|successor link=intel/cores/ice lake y
}}
'''Amber Lake Y''' ('''AML-Y''') is the name of the core for [[Intel]]'s extremly-low power line of processors based on the {{intel|Amber Lake|l=arch}} microarchitecture serving as a successor to {{intel|Kaby Lake Y|l=core}} core. These chips are primarily targeted towards 2-in-1s detachable, tablets, and computer sticks. Amber Lake Y processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm++ process]] and come at slightly higher clock frequencies.

== Overview ==
Amber Lake Y based processors are a single-chip solution - the [[chipset]] is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. AML-Y chips use {{intel|BGA-1515|Socket BGA-1515}}.

=== Common Features ===
All Amber Lake Y processors have the following:

* Dual-channel Memory
** Up to DDR3L-1600, LPDDR3-1866
** Up to 16 GiB
* 10-12x PCIe
* [[dual-core]] with 4 threads
* Everything up to SSE4.2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES) (not all Y models support {{x86|AVX}}/{{x86|AVX2}})
* Support [[RAID]], [[AHCI]], {{intel|Smart Response}}, [[High Definition Audio]], 6x [[USB 3.0]] ports, 6x [[USB 2.0]] ports, 4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]] 
* Graphics
** {{intel|HD Graphics 615}} ({{intel|Gen9.5|l=arch}} GT2)
** 3 independent displays supported
** Base frequency of 350 MHz
** Burst frequency of 900-1,050 MHz

{{clear}}

== Amber Lake Y Processors ==
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{{comp table start}}
<table class="comptable sortable tc15 tc16 tc17 tc18 tc19">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="18">List of Amber Lake Y Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Price, Family, %Cores, %Threads, %L3$, TDP, %Frequency, %Turbo, %Max Memory, Name, %Frequency, %Turbo}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Amber Lake Y]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?microprocessor family
 |?core count
 |?thread count
 |?l3$ size
 |?tdp
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?max memory#GiB
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |?has intel vpro technology
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Amber Lake Y]]}}
</table>
{{comp table end}}

== See also ==
[[File:kaby lake y (side).png|thumb|right|Side view of the AML-Y showing its thin profile.]]
{{intel coffee lake core see also}}
back image	+
designer	Intel +
first announced	June 4, 2018 +
first launched	August 28, 2018 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Amber Lake +
name	Amber Lake Y +
process	14 nm (0.014 μm, 1.4e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +