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Information for "intel/cores/alder lake s"
Basic information
Display title | Alder Lake S - Cores - Intel |
Default sort key | Alder Lake S, Intel |
Page length (in bytes) | 3,730 |
Page ID | 36531 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 18:40, 2 November 2021 |
Latest editor | 95.24.54.37 (talk) |
Date of latest edit | 19:56, 1 April 2025 |
Total number of edits | 6 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 1 |
Recent number of distinct authors | 1 |
Page properties
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Facts about "Alder Lake S - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | Intel + |
microarchitecture | Alder Lake + |
name | Alder Lake S + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |