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Difference between revisions of "intel/core i7/i7-7820x"
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'''Core i7-7820X''' is a {{arch|64}} [[octa-core]] high-performance [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]].  This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process]]. The i7-7820X operates at 3.6 GHz with a TDP of 140 W and a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.
 
'''Core i7-7820X''' is a {{arch|64}} [[octa-core]] high-performance [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]].  This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process]]. The i7-7820X operates at 3.6 GHz with a TDP of 140 W and a {{intel|Turbo Boost}} frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
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|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=8x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=11 MiB
 +
|l3 break=8x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 04:14, 31 May 2017

Template:mpu Core i7-7820X is a 64-bit octa-core high-performance x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i7-7820X operates at 3.6 GHz with a TDP of 140 W and a Turbo Boost frequency of 4.3 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back

L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back

L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back
Facts about "Core i7-7820X - Intel"
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +